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[X86] Add two combine rules to simplify dag nodes introduced during type legalization when promoting nodes with illegal vector type.
This patch teaches the backend how to simplify/canonicalize dag node
sequences normally introduced by the backend when promoting certain dag nodes
with illegal vector type.
This patch adds two new combine rules:
1) fold (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
(shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
2) fold (BINOP (shuffle (A, Undef, <Mask>)), (shuffle (B, Undef, <Mask>))) ->
(shuffle (BINOP A, B), Undef, <Mask>).
Both rules are only triggered on the type-legalized DAG.
In particular, rule 1. is a target specific combine rule that attempts
to sink a bitconvert into the operands of a binary operation.
Rule 2. is a target independet rule that attempts to move a shuffle
immediately after a binary operation.
llvm-svn: 209930
This commit is contained in:
Andrea Di Biagio
parent
8abf11ea97
commit
3a03708285
@ -10801,6 +10801,27 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
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}
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// Type legalization might introduce new shuffles in the DAG.
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// Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
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// -> (shuffle (VBinOp (A, B)), Undef, Mask).
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if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
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isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
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LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
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RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
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ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
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ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
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if (SVN0->getMask().equals(SVN1->getMask())) {
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EVT VT = N->getValueType(0);
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SDValue UndefVector = LHS.getOperand(1);
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SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
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LHS.getOperand(0), RHS.getOperand(0));
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AddUsersToWorkList(N);
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return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
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&SVN0->getMask()[0]);
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}
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}
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return SDValue();
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}
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@ -17495,6 +17495,8 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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SDLoc dl(N);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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EVT VT = N->getValueType(0);
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// Don't create instructions with illegal types after legalize types has run.
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@ -17507,6 +17509,57 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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N->getOpcode() == ISD::VECTOR_SHUFFLE)
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return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
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// During Type Legalization, when promoting illegal vector types,
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// the backend might introduce new shuffle dag nodes and bitcasts.
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//
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// This code performs the following transformation:
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// fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
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// (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
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//
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// We do this only if both the bitcast and the BINOP dag nodes have
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// one use. Also, perform this transformation only if the new binary
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// operation is legal. This is to avoid introducing dag nodes that
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// potentially need to be further expanded (or custom lowered) into a
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// less optimal sequence of dag nodes.
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if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
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N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
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N0.getOpcode() == ISD::BITCAST) {
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SDValue BC0 = N0.getOperand(0);
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EVT SVT = BC0.getValueType();
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unsigned Opcode = BC0.getOpcode();
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unsigned NumElts = VT.getVectorNumElements();
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if (BC0.hasOneUse() && SVT.isVector() &&
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SVT.getVectorNumElements() * 2 == NumElts &&
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TLI.isOperationLegal(Opcode, VT)) {
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bool CanFold = false;
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switch (Opcode) {
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default : break;
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case ISD::ADD :
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case ISD::FADD :
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case ISD::SUB :
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case ISD::FSUB :
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case ISD::MUL :
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case ISD::FMUL :
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CanFold = true;
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}
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unsigned SVTNumElts = SVT.getVectorNumElements();
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
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CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
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for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
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CanFold = SVOp->getMaskElt(i) < 0;
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if (CanFold) {
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SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
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SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
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SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
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return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
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}
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}
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}
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// Only handle 128 wide vector from here on.
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if (!VT.is128BitVector())
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return SDValue();
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273
test/CodeGen/X86/combine-64bit-vec-binop.ll
Normal file
273
test/CodeGen/X86/combine-64bit-vec-binop.ll
Normal file
@ -0,0 +1,273 @@
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; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=SSE41
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; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
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define double @test1_add(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%add = add <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %add to double
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ret double %3
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}
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; CHECK-LABEL: test1_add
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; SSE41: paddd
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; AVX: vpaddd
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; CHECK-NEXT: ret
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define double @test2_add(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%add = add <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %add to double
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ret double %3
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}
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; CHECK-LABEL: test2_add
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; SSE41: paddw
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; AVX: vpaddw
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; CHECK-NEXT: ret
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define double @test3_add(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%add = add <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %add to double
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ret double %3
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}
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; CHECK-LABEL: test3_add
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; SSE41: paddb
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; AVX: vpaddb
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; CHECK-NEXT: ret
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define double @test1_sub(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%sub = sub <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test1_sub
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; SSE41: psubd
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; AVX: vpsubd
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; CHECK-NEXT: ret
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define double @test2_sub(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%sub = sub <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test2_sub
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; SSE41: psubw
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; AVX: vpsubw
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; CHECK-NEXT: ret
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define double @test3_sub(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%sub = sub <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test3_sub
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; SSE41: psubb
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; AVX: vpsubb
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; CHECK-NEXT: ret
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define double @test1_mul(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%mul = mul <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test1_mul
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; SSE41: pmulld
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; AVX: vpmulld
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; CHECK-NEXT: ret
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define double @test2_mul(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%mul = mul <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test2_mul
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; SSE41: pmullw
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; AVX: vpmullw
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; CHECK-NEXT: ret
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; There is no legal ISD::MUL with type MVT::v8i16.
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define double @test3_mul(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%mul = mul <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test3_mul
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; CHECK: pmullw
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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define double @test1_and(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%and = and <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %and to double
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ret double %3
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}
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; CHECK-LABEL: test1_and
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; SSE41: andps
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; AVX: vandps
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; CHECK-NEXT: ret
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define double @test2_and(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%and = and <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %and to double
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ret double %3
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}
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; CHECK-LABEL: test2_and
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; SSE41: andps
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; AVX: vandps
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; CHECK-NEXT: ret
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define double @test3_and(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%and = and <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %and to double
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ret double %3
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}
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; CHECK-LABEL: test3_and
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; SSE41: andps
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; AVX: vandps
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; CHECK-NEXT: ret
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define double @test1_or(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%or = or <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %or to double
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ret double %3
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}
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; CHECK-LABEL: test1_or
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; SSE41: orps
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; AVX: vorps
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; CHECK-NEXT: ret
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define double @test2_or(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%or = or <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %or to double
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ret double %3
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}
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; CHECK-LABEL: test2_or
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; SSE41: orps
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; AVX: vorps
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; CHECK-NEXT: ret
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define double @test3_or(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%or = or <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %or to double
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ret double %3
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}
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; CHECK-LABEL: test3_or
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; SSE41: orps
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; AVX: vorps
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; CHECK-NEXT: ret
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define double @test1_xor(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%xor = xor <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %xor to double
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ret double %3
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}
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; CHECK-LABEL: test1_xor
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; SSE41: xorps
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; AVX: vxorps
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; CHECK-NEXT: ret
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define double @test2_xor(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%xor = xor <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %xor to double
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ret double %3
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}
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; CHECK-LABEL: test2_xor
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; SSE41: xorps
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; AVX: vxorps
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; CHECK-NEXT: ret
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define double @test3_xor(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%xor = xor <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %xor to double
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ret double %3
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}
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; CHECK-LABEL: test3_xor
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; SSE41: xorps
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; AVX: vxorps
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; CHECK-NEXT: ret
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define double @test_fadd(double %A, double %B) {
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%1 = bitcast double %A to <2 x float>
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%2 = bitcast double %B to <2 x float>
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%add = fadd <2 x float> %1, %2
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%3 = bitcast <2 x float> %add to double
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ret double %3
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}
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; CHECK-LABEL: test_fadd
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; SSE41: addps
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; AVX: vaddps
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; CHECK-NEXT: ret
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define double @test_fsub(double %A, double %B) {
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%1 = bitcast double %A to <2 x float>
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%2 = bitcast double %B to <2 x float>
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%sub = fsub <2 x float> %1, %2
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%3 = bitcast <2 x float> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test_fsub
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; SSE41: subps
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; AVX: vsubps
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; CHECK-NEXT: ret
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define double @test_fmul(double %A, double %B) {
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%1 = bitcast double %A to <2 x float>
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%2 = bitcast double %B to <2 x float>
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%mul = fmul <2 x float> %1, %2
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%3 = bitcast <2 x float> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test_fmul
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; SSE41: mulps
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; AVX: vmulps
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; CHECK-NEXT: ret
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@ -14,7 +14,7 @@ define double @test1(double %A) {
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; CHECK-LABEL: test1
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; CHECK-NOT: movsd
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; CHECK: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: paddd
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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@ -26,16 +26,9 @@ define double @test2(double %A, double %B) {
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%3 = bitcast <2 x i32> %add to double
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ret double %3
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}
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; FIXME: Ideally we should be able to fold the entire body of @test2 into a
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; single 'paddd %xmm1, %xmm0' instruction. At the moment we produce the
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; sequence pshufd+pshufd+paddq+pshufd.
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; CHECK-LABEL: test2
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; CHECK-NOT: movsd
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; CHECK: pshufd
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: pshufd
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; CHECK: paddd
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; CHECK-NEXT: ret
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@ -91,7 +84,7 @@ define double @test6(double %A) {
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; CHECK-LABEL: test6
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; CHECK-NOT: movsd
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; CHECK: punpcklwd
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; CHECK-NEXT: paddd
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; CHECK-NEXT: paddw
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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@ -103,16 +96,10 @@ define double @test7(double %A, double %B) {
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%3 = bitcast <4 x i16> %add to double
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ret double %3
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}
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; FIXME: Ideally we should be able to fold the entire body of @test7 into a
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; single 'paddw %xmm1, %xmm0' instruction. At the moment we produce the
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; sequence pshufd+pshufd+paddd+pshufd.
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; CHECK-LABEL: test7
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; CHECK-NOT: movsd
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||||
; CHECK: punpcklwd
|
||||
; CHECK-NEXT: punpcklwd
|
||||
; CHECK-NEXT: paddd
|
||||
; CHECK-NEXT: pshufb
|
||||
; CHECK-NOT: punpcklwd
|
||||
; CHECK: paddw
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
|
||||
@ -129,7 +116,7 @@ define double @test8(double %A) {
|
||||
; CHECK-LABEL: test8
|
||||
; CHECK-NOT: movsd
|
||||
; CHECK: punpcklbw
|
||||
; CHECK-NEXT: paddw
|
||||
; CHECK-NEXT: paddb
|
||||
; CHECK-NEXT: pshufb
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
@ -141,15 +128,9 @@ define double @test9(double %A, double %B) {
|
||||
%3 = bitcast <8 x i8> %add to double
|
||||
ret double %3
|
||||
}
|
||||
; FIXME: Ideally we should be able to fold the entire body of @test9 into a
|
||||
; single 'paddb %xmm1, %xmm0' instruction. At the moment we produce the
|
||||
; sequence pshufd+pshufd+paddw+pshufd.
|
||||
|
||||
; CHECK-LABEL: test9
|
||||
; CHECK-NOT: movsd
|
||||
; CHECK: punpcklbw
|
||||
; CHECK-NEXT: punpcklbw
|
||||
; CHECK-NEXT: paddw
|
||||
; CHECK-NEXT: pshufb
|
||||
; CHECK-NOT: punpcklbw
|
||||
; CHECK: paddb
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user