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Adds code to PPC ISEL lowering to recognize half-word inserts from vector_shuffles, and use P9 shift and vector insert instructions instead of vperm.
Differential Revision: https://reviews.llvm.org/D34160 llvm-svn: 317111
This commit is contained in:
Graham Yiu
parent
dcf81a0c5e
commit
3a093847f1
@ -114,6 +114,8 @@ cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
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STATISTIC(NumTailCalls, "Number of tail calls");
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STATISTIC(NumSiblingCalls, "Number of sibling calls");
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static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
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// FIXME: Remove this once the bug has been fixed!
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extern cl::opt<bool> ANDIGlueBug;
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@ -7886,6 +7888,118 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
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return DAG.getNode(ISD::BITCAST, dl, VT, T);
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}
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/// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be handled
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/// by the VINSERTH instruction introduced in ISA 3.0, else just return default
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/// SDValue.
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SDValue PPCTargetLowering::lowerToVINSERTH(ShuffleVectorSDNode *N,
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SelectionDAG &DAG) const {
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const unsigned NumHalfWords = 8;
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const unsigned BytesInVector = NumHalfWords * 2;
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// Check that the shuffle is on half-words.
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if (!isNByteElemShuffleMask(N, 2, 1))
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return SDValue();
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bool IsLE = Subtarget.isLittleEndian();
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SDLoc dl(N);
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SDValue V1 = N->getOperand(0);
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SDValue V2 = N->getOperand(1);
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unsigned ShiftElts = 0, InsertAtByte = 0;
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bool Swap = false;
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// Shifts required to get the half-word we want at element 3.
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unsigned LittleEndianShifts[] = {4, 3, 2, 1, 0, 7, 6, 5};
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unsigned BigEndianShifts[] = {5, 6, 7, 0, 1, 2, 3, 4};
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uint32_t Mask = 0;
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uint32_t OriginalOrderLow = 0x1234567;
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uint32_t OriginalOrderHigh = 0x89ABCDEF;
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// Now we look at mask elements 0,2,4,6,8,10,12,14. Pack the mask into a
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// 32-bit space, only need 4-bit nibbles per element.
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for (unsigned i = 0; i < NumHalfWords; ++i) {
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unsigned MaskShift = (NumHalfWords - 1 - i) * 4;
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Mask |= ((uint32_t)(N->getMaskElt(i * 2) / 2) << MaskShift);
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}
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// For each mask element, find out if we're just inserting something
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// from V2 into V1 or vice versa. Possible permutations inserting an element
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// from V2 into V1:
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// X, 1, 2, 3, 4, 5, 6, 7
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// 0, X, 2, 3, 4, 5, 6, 7
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// 0, 1, X, 3, 4, 5, 6, 7
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// 0, 1, 2, X, 4, 5, 6, 7
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// 0, 1, 2, 3, X, 5, 6, 7
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// 0, 1, 2, 3, 4, X, 6, 7
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// 0, 1, 2, 3, 4, 5, X, 7
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// 0, 1, 2, 3, 4, 5, 6, X
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// Inserting from V1 into V2 will be similar, except mask range will be [8,15].
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bool FoundCandidate = false;
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// Go through the mask of half-words to find an element that's being moved
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// from one vector to the other.
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for (unsigned i = 0; i < NumHalfWords; ++i) {
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unsigned MaskShift = (NumHalfWords - 1 - i) * 4;
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uint32_t MaskOneElt = (Mask >> MaskShift) & 0xF;
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uint32_t MaskOtherElts = ~(0xF << MaskShift);
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uint32_t TargetOrder = 0x0;
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// If both vector operands for the shuffle are the same vector, the mask
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// will contain only elements from the first one and the second one will be
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// undef.
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if (V2.isUndef()) {
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ShiftElts = 0;
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unsigned VINSERTHSrcElem = IsLE ? 4 : 3;
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TargetOrder = OriginalOrderLow;
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Swap = false;
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// Skip if not the correct element or mask of other elements don't equal
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// to our expected order.
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if (MaskOneElt == VINSERTHSrcElem &&
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(Mask & MaskOtherElts) == (TargetOrder & MaskOtherElts)) {
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InsertAtByte = IsLE ? BytesInVector - (i + 1) * 2 : i * 2;
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FoundCandidate = true;
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break;
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}
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} else { // If both operands are defined.
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// Target order is [8,15] if the current mask is between [0,7].
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TargetOrder =
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(MaskOneElt < NumHalfWords) ? OriginalOrderHigh : OriginalOrderLow;
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// Skip if mask of other elements don't equal our expected order.
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if ((Mask & MaskOtherElts) == (TargetOrder & MaskOtherElts)) {
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// We only need the last 3 bits for the number of shifts.
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ShiftElts = IsLE ? LittleEndianShifts[MaskOneElt & 0x7]
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: BigEndianShifts[MaskOneElt & 0x7];
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InsertAtByte = IsLE ? BytesInVector - (i + 1) * 2 : i * 2;
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Swap = MaskOneElt < NumHalfWords;
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FoundCandidate = true;
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break;
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}
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}
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}
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if (!FoundCandidate)
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return SDValue();
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// Candidate found, construct the proper SDAG sequence with VINSERTH,
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// optionally with VECSHL if shift is required.
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if (Swap)
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std::swap(V1, V2);
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if (V2.isUndef())
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V2 = V1;
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SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
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if (ShiftElts) {
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// Double ShiftElts because we're left shifting on v16i8 type.
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SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2,
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DAG.getConstant(2 * ShiftElts, dl, MVT::i32));
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SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, Shl);
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SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2,
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DAG.getConstant(InsertAtByte, dl, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
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}
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SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
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SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2,
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DAG.getConstant(InsertAtByte, dl, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
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}
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/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
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/// is a shuffle we can handle in a single instruction, return it. Otherwise,
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/// return the code it can be lowered into. Worst case, it can always be
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@ -7920,6 +8034,11 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
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}
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if (Subtarget.hasP9Altivec()) {
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SDValue NewISDNode = lowerToVINSERTH(SVOp, DAG);
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if (NewISDNode)
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return NewISDNode;
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}
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if (Subtarget.hasVSX() &&
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PPC::isXXSLDWIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) {
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@ -1072,7 +1072,14 @@ namespace llvm {
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SDValue
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combineElementTruncationToVectorTruncation(SDNode *N,
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DAGCombinerInfo &DCI) const;
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};
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/// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
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/// handled by the VINSERTH instruction introduced in ISA 3.0. This is
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/// essentially any shuffle of v8i16 vectors that just inserts one element
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/// from one vector into the other.
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SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
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}; // end class PPCTargetLowering
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namespace PPC {
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@ -477,10 +477,10 @@ def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
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def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
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// Shuffles.
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def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
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def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH),
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"vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
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[(set v16i8:$vD,
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(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
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[(set v16i8:$vD,
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(PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>;
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// VX-Form instructions. AltiVec arithmetic ops.
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let isCommutable = 1 in {
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@ -908,6 +908,9 @@ def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
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(VPKUWUM $vA, $vA)>;
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def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
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(VPKUHUM $vA, $vA)>;
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def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB),
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(VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>;
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// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
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// These fragments are matched for little-endian, where the inputs must
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@ -1310,7 +1313,12 @@ def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
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// Vector Insert Element Instructions
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def VINSERTB : VX1_VT5_UIM5_VB5<781, "vinsertb", []>;
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def VINSERTH : VX1_VT5_UIM5_VB5<845, "vinserth", []>;
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def VINSERTH : VXForm_1<845, (outs vrrc:$vD),
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(ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB),
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"vinserth $vD, $vB, $UIM", IIC_VecGeneral,
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[(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB,
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imm32SExt16:$UIM))]>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
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def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
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300
test/CodeGen/PowerPC/p9-vinsert-vextract.ll
Normal file
300
test/CodeGen/PowerPC/p9-vinsert-vextract.ll
Normal file
@ -0,0 +1,300 @@
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
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; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
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; The following testcases take one halfword element from the second vector and
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; inserts it at various locations in the first vector
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define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_0_8
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; CHECK: vsldoi 3, 3, 3, 8
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; CHECK: vinserth 2, 3, 14
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; CHECK-BE-LABEL: shuffle_vector_halfword_0_8
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; CHECK-BE: vsldoi 3, 3, 3, 10
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; CHECK-BE: vinserth 2, 3, 0
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_1_15
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; CHECK: vsldoi 3, 3, 3, 10
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; CHECK: vinserth 2, 3, 12
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; CHECK-BE-LABEL: shuffle_vector_halfword_1_15
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; CHECK-BE: vsldoi 3, 3, 3, 8
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; CHECK-BE: vinserth 2, 3, 2
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_2_9
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; CHECK: vsldoi 3, 3, 3, 6
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; CHECK: vinserth 2, 3, 10
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; CHECK-BE-LABEL: shuffle_vector_halfword_2_9
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; CHECK-BE: vsldoi 3, 3, 3, 12
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; CHECK-BE: vinserth 2, 3, 4
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_3_13
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; CHECK: vsldoi 3, 3, 3, 14
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; CHECK: vinserth 2, 3, 8
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; CHECK-BE-LABEL: shuffle_vector_halfword_3_13
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; CHECK-BE: vsldoi 3, 3, 3, 4
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; CHECK-BE: vinserth 2, 3, 6
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_4_10
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; CHECK: vsldoi 3, 3, 3, 4
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; CHECK: vinserth 2, 3, 6
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; CHECK-BE-LABEL: shuffle_vector_halfword_4_10
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; CHECK-BE: vsldoi 3, 3, 3, 14
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; CHECK-BE: vinserth 2, 3, 8
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_5_14
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; CHECK: vsldoi 3, 3, 3, 12
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; CHECK: vinserth 2, 3, 4
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; CHECK-BE-LABEL: shuffle_vector_halfword_5_14
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; CHECK-BE: vsldoi 3, 3, 3, 6
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; CHECK-BE: vinserth 2, 3, 10
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_6_11
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; CHECK: vsldoi 3, 3, 3, 2
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; CHECK: vinserth 2, 3, 2
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; CHECK-BE-LABEL: shuffle_vector_halfword_6_11
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; CHECK-BE: vinserth 2, 3, 12
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_7_12
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; CHECK: vinserth 2, 3, 0
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; CHECK-BE-LABEL: shuffle_vector_halfword_7_12
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; CHECK-BE: vsldoi 3, 3, 3, 2
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; CHECK-BE: vinserth 2, 3, 14
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12>
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ret <8 x i16> %vecins
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}
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define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_8_1
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; CHECK: vsldoi 2, 2, 2, 6
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; CHECK: vinserth 3, 2, 14
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; CHECK: vmr 2, 3
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; CHECK-BE-LABEL: shuffle_vector_halfword_8_1
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; CHECK-BE: vsldoi 2, 2, 2, 12
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; CHECK-BE: vinserth 3, 2, 0
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; CHECK-BE: vmr 2, 3
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i16> %vecins
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}
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; The following testcases take one halfword element from the first vector and
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; inserts it at various locations in the second vector
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define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {
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entry:
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; CHECK-LABEL: shuffle_vector_halfword_9_7
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; CHECK: vsldoi 2, 2, 2, 10
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; CHECK: vinserth 3, 2, 12
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; CHECK: vmr 2, 3
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; CHECK-BE-LABEL: shuffle_vector_halfword_9_7
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; CHECK-BE: vsldoi 2, 2, 2, 8
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; CHECK-BE: vinserth 3, 2, 2
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; CHECK-BE: vmr 2, 3
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%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i16> %vecins
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}
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|
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define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_10_4
|
||||
; CHECK: vinserth 3, 2, 10
|
||||
; CHECK: vmr 2, 3
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_10_4
|
||||
; CHECK-BE: vsldoi 2, 2, 2, 2
|
||||
; CHECK-BE: vinserth 3, 2, 4
|
||||
; CHECK-BE: vmr 2, 3
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_11_2
|
||||
; CHECK: vsldoi 2, 2, 2, 4
|
||||
; CHECK: vinserth 3, 2, 8
|
||||
; CHECK: vmr 2, 3
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_11_2
|
||||
; CHECK-BE: vsldoi 2, 2, 2, 14
|
||||
; CHECK-BE: vinserth 3, 2, 6
|
||||
; CHECK-BE: vmr 2, 3
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_12_6
|
||||
; CHECK: vsldoi 2, 2, 2, 12
|
||||
; CHECK: vinserth 3, 2, 6
|
||||
; CHECK: vmr 2, 3
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_12_6
|
||||
; CHECK-BE: vsldoi 2, 2, 2, 6
|
||||
; CHECK-BE: vinserth 3, 2, 8
|
||||
; CHECK-BE: vmr 2, 3
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_13_3
|
||||
; CHECK: vsldoi 2, 2, 2, 2
|
||||
; CHECK: vinserth 3, 2, 4
|
||||
; CHECK: vmr 2, 3
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_13_3
|
||||
; CHECK-BE: vinserth 3, 2, 10
|
||||
; CHECK-BE: vmr 2, 3
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_14_5
|
||||
; CHECK: vsldoi 2, 2, 2, 14
|
||||
; CHECK: vinserth 3, 2, 2
|
||||
; CHECK: vmr 2, 3
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_14_5
|
||||
; CHECK-BE: vsldoi 2, 2, 2, 4
|
||||
; CHECK-BE: vinserth 3, 2, 12
|
||||
; CHECK-BE: vmr 2, 3
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_15_0
|
||||
; CHECK: vsldoi 2, 2, 2, 8
|
||||
; CHECK: vinserth 3, 2, 0
|
||||
; CHECK: vmr 2, 3
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_15_0
|
||||
; CHECK-BE: vsldoi 2, 2, 2, 10
|
||||
; CHECK-BE: vinserth 3, 2, 14
|
||||
; CHECK-BE: vmr 2, 3
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
; The following testcases use the same vector in both arguments of the
|
||||
; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one
|
||||
; we're attempting to insert, then we can use the vector insert instruction
|
||||
define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_0_4
|
||||
; CHECK: vinserth 2, 2, 14
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_0_4
|
||||
; CHECK-BE-NOT: vinserth
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_1_3
|
||||
; CHECK-NOT: vinserth
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_1_3
|
||||
; CHECK-BE: vinserth 2, 2, 2
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_2_3
|
||||
; CHECK-NOT: vinserth
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_2_3
|
||||
; CHECK-BE: vinserth 2, 2, 4
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_3_4
|
||||
; CHECK: vinserth 2, 2, 8
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_3_4
|
||||
; CHECK-BE-NOT: vinserth
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_4_3
|
||||
; CHECK-NOT: vinserth
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_4_3
|
||||
; CHECK-BE: vinserth 2, 2, 8
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_5_3
|
||||
; CHECK-NOT: vinserth
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_5_3
|
||||
; CHECK-BE: vinserth 2, 2, 10
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_6_4
|
||||
; CHECK: vinserth 2, 2, 2
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_6_4
|
||||
; CHECK-BE-NOT: vinserth
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: shuffle_vector_halfword_7_4
|
||||
; CHECK: vinserth 2, 2, 0
|
||||
; CHECK-BE-LABEL: shuffle_vector_halfword_7_4
|
||||
; CHECK-BE-NOT: vinserth
|
||||
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
|
||||
ret <8 x i16> %vecins
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user