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Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands
This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
This commit is contained in:
parent
409fc25f58
commit
3a098791a4
@ -143,7 +143,6 @@ public:
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enum NearMissKind {
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NoNearMiss,
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NearMissOperand,
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NearMissMultipleOperands,
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NearMissFeature,
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NearMissPredicate,
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NearMissTooFewOperands,
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@ -190,13 +189,6 @@ public:
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return Result;
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}
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static NearMissInfo getMissedMultipleOperands(unsigned Opcode) {
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NearMissInfo Result;
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Result.Kind = NearMissMultipleOperands;
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Result.MissedOperand.Opcode = Opcode;
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return Result;
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}
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// The instruction encoding is not valid because it expects more operands
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// than were parsed. OperandClass is the class of the expected operand that
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// was not provided. Opcode is the instruction encoding.
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@ -216,41 +208,34 @@ public:
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// Feature flags required by the instruction, that the current target does
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// not have.
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uint64_t getFeatures() const {
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assert(Kind == NearMissFeature &&
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"near-miss does not have an associated target feature");
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assert(Kind == NearMissFeature);
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return Features;
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}
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// Error code returned by the target predicate when validating this
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// instruction encoding.
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unsigned getPredicateError() const {
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assert(Kind == NearMissPredicate &&
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"near-miss does not have an associated predicate error");
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assert(Kind == NearMissPredicate);
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return PredicateError;
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}
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// MatchClassKind of the operand that we expected to see.
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unsigned getOperandClass() const {
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assert((Kind == NearMissOperand || Kind == NearMissTooFewOperands) &&
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"near-miss does not have an associated operand class");
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assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands);
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return MissedOperand.Class;
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}
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// Opcode of the encoding we were trying to match.
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unsigned getOpcode() const {
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assert((Kind == NearMissOperand || Kind == NearMissTooFewOperands ||
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Kind == NearMissMultipleOperands) &&
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"near-miss does not have an associated opcode");
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assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands);
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return MissedOperand.Opcode;
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}
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// Error code returned when validating the operand.
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unsigned getOperandError() const {
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assert(Kind == NearMissOperand &&
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"near-miss does not have an associated operand error");
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assert(Kind == NearMissOperand);
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return MissedOperand.Error;
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}
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// Index of the actual operand we were trying to match in the list of parsed
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// operands.
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unsigned getOperandIndex() const {
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assert(Kind == NearMissOperand &&
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"near-miss does not have an associated operand index");
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assert(Kind == NearMissOperand);
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return MissedOperand.Index;
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}
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@ -10134,7 +10134,6 @@ ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
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std::multimap<unsigned, unsigned> OperandMissesSeen;
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SmallSet<uint64_t, 4> FeatureMissesSeen;
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bool ReportedTooFewOperands = false;
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bool HaveMultipleBadOperands = false;
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// Process the near-misses in reverse order, so that we see more general ones
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// first, and so can avoid emitting more specific ones.
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@ -10254,12 +10253,6 @@ ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
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NearMissesOut.emplace_back(Message);
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break;
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}
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case NearMissInfo::NearMissMultipleOperands: {
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// Just record the fact that we have seen this, we will use it as a
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// fall-back if we don't find a better operand error to report.
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HaveMultipleBadOperands = true;
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break;
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}
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case NearMissInfo::NearMissTooFewOperands: {
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if (!ReportedTooFewOperands) {
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SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
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@ -10275,16 +10268,6 @@ ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
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break;
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}
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}
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// If there is an encoding that missed on multiple operands (but matched the
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// target features and early predicate), but we haven't been able to emit a
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// more specific error for any operands, emit a generic error. This lets the
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// user know that the mnemonic exists, and that some combination of operands
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// would work for the current target.
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if (HaveMultipleBadOperands && NearMissesOut.empty()) {
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NearMissesOut.emplace_back(NearMissMessage{
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IDLoc, StringRef("invalid operands for instruction")});
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}
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}
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void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
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@ -1,4 +1,4 @@
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RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
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@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
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@ RUN: not llvm-mc -triple=armv8 < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ -164,7 +164,7 @@
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@ CHECK-ERRORS: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V8: error: invalid operands for instruction
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@ CHECK-ERRORS-V8: invalid instruction
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@ CHECK-ERRORS-V8: too many operands for instruction
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@ CHECK-ERRORS: operand must be an immediate in the range [0,15]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
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@ -208,7 +208,7 @@
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@ CHECK-ERRORS: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V8: error: invalid operands for instruction
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@ CHECK-ERRORS-V8: invalid instruction
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V8: too many operands for instruction
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@ CHECK-ERRORS: operand must be an immediate in the range [0,15]
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@ -35,38 +35,38 @@
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@ V8: error: invalid instruction
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vseleq.f32 s0, d2, d1
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vselgt.f64 s3, s2, s1
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@ V8: error: invalid operand for instruction
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vselgt.f32 s0, q3, q1
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vselgt.f64 q0, s3, q1
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vmaxnm.f32 s0, d2, d1
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vminnm.f64 s3, s2, s1
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@ V8: error: invalid operand for instruction
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vmaxnm.f32 s0, q3, q1
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vmaxnm.f64 q0, s3, q1
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vmaxnmgt.f64 q0, s3, q1
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@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
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vcvta.s32.f64 d3, s2
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vcvtp.s32.f32 d3, s2
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@ V8: error: operand must be a register in range [s0, s31]
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vcvtn.u32.f64 d3, s2
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vcvtm.u32.f32 d3, s2
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@ V8: error: operand must be a register in range [s0, s31]
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vcvtnge.u32.f64 d3, s2
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@ V8: error: instruction 'vcvtn' is not predicable, but condition code specified
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vcvtbgt.f64.f16 q0, d3
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vcvttlt.f64.f16 s0, s3
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@ V8: error: invalid instruction, any one of the following would fix this:
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@ V8: note: operand must be a register in range [d0, d31]
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@ -79,12 +79,12 @@ vcvtthi.f16.f64 q0, d3
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@ V8: error: operand must be a register in range [s0, s31]
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vrintrlo.f32.f32 d3, q0
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vrintxcs.f32.f32 d3, d0
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vrinta.f64.f64 s3, q0
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@ V8: error: invalid operands for instruction
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@ V8: error: invalid instruction
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vrintn.f32.f32 d3, d0
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@ V8: error: instruction requires: NEON
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vrintp.f32 q3, q0
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@ -1,9 +1,9 @@
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@ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s
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vmaxnm.f32 s4, d5, q1
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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vmaxnm.f64.f64 s4, d5, q1
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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vmaxnmge.f64.f64 s4, d5, q1
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@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
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@ -12,12 +12,12 @@ vcvta.s32.f32 s1, s2
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vcvtp.u32.f32 s1, d2
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@ CHECK: error: operand must be a register in range [d0, d31]
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vcvtp.f32.u32 d1, q2
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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vcvtplo.f32.u32 s1, s2
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@ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified
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vrinta.f64.f64 s3, d12
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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vrintn.f32 d3, q12
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: note: operand must be a register in range [d0, d31]
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@ -50,7 +50,7 @@ sha1heq.32 q0, q1
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@ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
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sha1c.32 s0, d1, q2
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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sha1m.32 q0, s1, q2
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha1p.32 s0, q1, q2
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@ -62,12 +62,12 @@ sha256h.32 q0, s1, q2
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sha256h2.32 q0, q1, s2
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha256su1.32 s0, d1, q2
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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sha256su1lt.32 q0, d1, q2
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@ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
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vmull.p64 q0, s1, s3
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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vmull.p64 s1, d2, d3
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@ CHECK: error: operand must be a register in range [q0, q15]
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vmullge.p64 q0, d16, d17
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@ -2,18 +2,18 @@
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.text
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.arm
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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@ CHECK: ldrd r12, [r0, #512]
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ldrd r12, [r0, #512]
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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@ CHECK: strd r12, [r0, #512]
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strd r12, [r0, #512]
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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@ CHECK: ldrd r1, [r0, #512]
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ldrd r1, [r0, #512]
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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@ CHECK: strd r1, [r0, #512]
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strd r1, [r0, #512]
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@ -10,9 +10,9 @@
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strd r0
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@ CHECK: error: too few operands for instruction
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ldrd r0
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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strd s0, [r0]
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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ldrd s0, [r0]
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.arm
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@ CHECK: error: too few operands for instruction
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@ -23,7 +23,7 @@
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strd r0
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@ CHECK: error: too few operands for instruction
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ldrd r0
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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strd s0, [r0]
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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ldrd s0, [r0]
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@ -8,20 +8,20 @@
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.arm
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// V7: error: invalid operands for instruction
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// V7: error: invalid instruction
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// V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1]
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ldrd r12, [r0, #32]
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// V7: error: invalid operands for instruction
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// V7: error: invalid instruction
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// V8: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1]
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strd r12, [r0, #32]
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.thumb
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// V7: error: invalid operands for instruction
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// V7: error: invalid instruction
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// V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xe9,0x08,0xcd]
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ldrd r12, [r0, #32]
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// V7: error: invalid operands for instruction
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// V7: error: invalid instruction
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// V8: strd r12, sp, [r0, #32] @ encoding: [0xc0,0xe9,0x08,0xcd]
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strd r12, [r0, #32]
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@ -2,10 +2,10 @@
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.text
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.thumb
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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@ CHECK: ldrd r12, [r0, #512]
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ldrd r12, [r0, #512]
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@ CHECK: error: invalid operands for instruction
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@ CHECK: error: invalid instruction
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@ CHECK: strd r12, [r0, #512]
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strd r12, [r0, #512]
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@ -19,7 +19,7 @@
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// CHECK-NEXT: movs r0, pc
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// CHECK: note: invalid operand for instruction
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// CHECK-NEXT: movs r0, pc
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// CHECK: error: invalid operands for instruction
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// CHECK: error: invalid instruction
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// CHECK-NEXT: movs pc, pc
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// mov.w selects t2MOVr
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@ -32,7 +32,7 @@
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// CHECK-NEXT: mov.w r0, pc
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// CHECK: note: invalid operand for instruction
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// CHECK-NEXT: mov.w r0, pc
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// CHECK: error: invalid operands for instruction
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// CHECK: error: invalid instruction
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// CHECK-NEXT: mov.w pc, pc
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// movs.w selects t2MOVr
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@ -45,7 +45,7 @@
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// CHECK-NEXT: movs.w r0, pc
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// CHECK: note: invalid operand for instruction
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// CHECK-NEXT: movs.w r0, pc
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// CHECK: error: invalid operands for instruction
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// CHECK: error: invalid instruction
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// CHECK-NEXT: movs.w pc, pc
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@ -43,7 +43,7 @@
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@ CHECK-ERRORS: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V8: error: invalid operands for instruction
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@ CHECK-ERRORS-V8: invalid instruction
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@ CHECK-ERRORS-V8: too many operands for instruction
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@ CHECK-ERRORS: operand must be an immediate in the range [0,15]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
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@ -91,11 +91,8 @@ foo2:
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and sp, r1, #80008000
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and pc, r1, #80008000
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@ CHECK-ERRORS-V7: error: invalid operands for instruction
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@ CHECK-ERRORS-V8: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS-V8: note: invalid operand for instruction
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@ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]
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@ CHECK-ERRORS: error: invalid operands for instruction
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@ CHECK-ERRORS: error: invalid instruction
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@ CHECK-ERRORS: error: invalid instruction
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ssat r0, #1, r0, asr #32
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usat r0, #1, r0, asr #32
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@ -132,7 +129,7 @@ foo2:
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: instruction requires: arm-mode
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operands for instruction
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@ CHECK-ERRORS: error: invalid instruction
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS: note: instruction requires: arm-mode
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@ -6,7 +6,7 @@
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@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
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@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
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@ THUMB_V7EM-ERRORS: error: invalid operands for instruction
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@ THUMB_V7EM-ERRORS: error: invalid instruction
|
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@ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17
|
||||
vfma.f64 d16, d18, d17
|
||||
|
||||
@ -17,7 +17,7 @@ vfma.f32 s2, s4, s0
|
||||
|
||||
@ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
|
||||
@ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
|
||||
@ THUMB_V7EM-ERRORS: error: invalid operands for instruction
|
||||
@ THUMB_V7EM-ERRORS: error: invalid instruction
|
||||
@ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17
|
||||
vfma.f32 d16, d18, d17
|
||||
|
||||
@ -29,7 +29,7 @@ vfma.f32 q2, q4, q0
|
||||
|
||||
@ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee]
|
||||
@ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b]
|
||||
@ THUMB_V7EM-ERRORS: error: invalid operands for instruction
|
||||
@ THUMB_V7EM-ERRORS: error: invalid instruction
|
||||
@ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17
|
||||
vfnma.f64 d16, d18, d17
|
||||
|
||||
@ -40,7 +40,7 @@ vfnma.f32 s2, s4, s0
|
||||
|
||||
@ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee]
|
||||
@ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b]
|
||||
@ THUMB_V7EM-ERRORS: error: invalid operands for instruction
|
||||
@ THUMB_V7EM-ERRORS: error: invalid instruction
|
||||
@ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17
|
||||
vfms.f64 d16, d18, d17
|
||||
|
||||
@ -51,7 +51,7 @@ vfms.f32 s2, s4, s0
|
||||
|
||||
@ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2]
|
||||
@ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c]
|
||||
@ THUMB_V7EM-ERRORS: error: invalid operands for instruction
|
||||
@ THUMB_V7EM-ERRORS: error: invalid instruction
|
||||
@ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17
|
||||
vfms.f32 d16, d18, d17
|
||||
|
||||
@ -63,7 +63,7 @@ vfms.f32 q2, q4, q0
|
||||
|
||||
@ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee]
|
||||
@ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b]
|
||||
@ THUMB_V7EM-ERRORS: error: invalid operands for instruction
|
||||
@ THUMB_V7EM-ERRORS: error: invalid instruction
|
||||
@ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17
|
||||
vfnms.f64 d16, d18, d17
|
||||
|
||||
|
@ -3275,6 +3275,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";
|
||||
OS << " NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();\n";
|
||||
OS << " NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();\n";
|
||||
OS << " bool MultipleInvalidOperands = false;\n";
|
||||
}
|
||||
|
||||
if (HasMnemonicFirst) {
|
||||
@ -3313,12 +3314,11 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " OperandNearMiss =\n";
|
||||
OS << " NearMissInfo::getTooFewOperands(Formal, it->Opcode);\n";
|
||||
OS << " } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {\n";
|
||||
OS << " // An invalid operand plus a missing one at the end are reported the\n";
|
||||
OS << " // same way as multiple invalid operands.\n";
|
||||
OS << " // If more than one operand is invalid, give up on this match entry.\n";
|
||||
OS << " DEBUG_WITH_TYPE(\n";
|
||||
OS << " \"asm-matcher\",\n";
|
||||
OS << " dbgs() << \"second invalid operand, giving up on this opcode\\n\");\n";
|
||||
OS << " OperandNearMiss = NearMissInfo::getMissedMultipleOperands(it->Opcode);\n";
|
||||
OS << " MultipleInvalidOperands = true;\n";
|
||||
OS << " break;\n";
|
||||
OS << " }\n";
|
||||
OS << " } else {\n";
|
||||
@ -3387,7 +3387,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " DEBUG_WITH_TYPE(\n";
|
||||
OS << " \"asm-matcher\",\n";
|
||||
OS << " dbgs() << \"second operand mismatch, skipping this opcode\\n\");\n";
|
||||
OS << " OperandNearMiss = NearMissInfo::getMissedMultipleOperands(it->Opcode);\n";
|
||||
OS << " MultipleInvalidOperands = true;\n";
|
||||
OS << " break;\n";
|
||||
OS << " }\n";
|
||||
OS << " }\n\n";
|
||||
@ -3409,14 +3409,15 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " }\n\n";
|
||||
}
|
||||
|
||||
if (!ReportMultipleNearMisses) {
|
||||
if (ReportMultipleNearMisses)
|
||||
OS << " if (MultipleInvalidOperands) {\n";
|
||||
else
|
||||
OS << " if (!OperandsValid) {\n";
|
||||
OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
|
||||
OS << " \"operand mismatches, ignoring \"\n";
|
||||
OS << " \"this opcode\\n\");\n";
|
||||
OS << " continue;\n";
|
||||
OS << " }\n";
|
||||
}
|
||||
OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
|
||||
OS << " \"operand mismatches, ignoring \"\n";
|
||||
OS << " \"this opcode\\n\");\n";
|
||||
OS << " continue;\n";
|
||||
OS << " }\n";
|
||||
|
||||
// Emit check that the required features are available.
|
||||
OS << " if ((AvailableFeatures & it->RequiredFeatures) "
|
||||
|
Loading…
Reference in New Issue
Block a user