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[AMDGPU] Fix PC register mapping in wave32 mode

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Summary:
The PC_32 DWARF register is for a 32-bit process address space which we
don't implement in AMDGCN; another way of putting this is that the size
of the PC register is not a function of the wavefront size. If we ever
implement a 32-bit process address space we will need to add two more
DwarfFlavours i.e. we will need to represent the product of (wave32,
wave64) x (64-bit address space, 32-bit address space).

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76732
This commit is contained in:
Scott Linder 2020-03-24 17:24:49 -04:00
parent 8238e95412
commit 3a0c436c93
3 changed files with 6 additions and 5 deletions
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2
lib/Target/AMDGPU/SIRegisterInfo.td
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@ -103,7 +103,7 @@ def FP_REG : SIReg<"fp", 0>;
def SP_REG : SIReg<"sp", 0>;
// Pseudo-register to represent the program-counter DWARF register.
def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 0]> {
def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> {
// There is no physical register corresponding to a "program counter", but
// we need to encode the concept in debug information in order to represent
// things like the return value in unwind information.

4
unittests/MC/AMDGPU/DwarfRegMappings.cpp
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@ -65,10 +65,10 @@ TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
if (TM && TM->getMCRegisterInfo()) {
auto MRI = TM->getMCRegisterInfo();
// Wave32 Dwarf register mapping test numbers
// PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
// A0 => 2048, A255 => 2303
for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
}

5
unittests/Target/AMDGPU/DwarfRegMappings.cpp
View File

@ -75,10 +75,11 @@ TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
auto MRI = ST.getRegisterInfo();
if (MRI) {
// Wave32 Dwarf register mapping test numbers
// PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
// A0 => 2048, A255 => 2303
for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
for (int llvmReg :
{16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
}