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[PowerPC] Implement Vector signed/unsigned __int128 overloads for the comparison builtins
This patch implements Vector signed/unsigned __int128 overloads for the comparison builtins. Differential Revision: https://reviews.llvm.org/D87804
This commit is contained in:
Albion Fung
parent
a8a8abc4ed
commit
3a1a7e4141
@ -361,6 +361,16 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vcmpequq : GCCBuiltin<"__builtin_altivec_vcmpequq">,
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Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vcmpgtsq : GCCBuiltin<"__builtin_altivec_vcmpgtsq">,
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Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vcmpgtuq : GCCBuiltin<"__builtin_altivec_vcmpgtuq">,
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Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty],
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[IntrNoMem]>;
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// Predicate Comparisons. The first operand specifies interpretation of CR6.
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def int_ppc_altivec_vcmpbfp_p : GCCBuiltin<"__builtin_altivec_vcmpbfp_p">,
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Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4f32_ty,llvm_v4f32_ty],
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@ -3948,7 +3948,8 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
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// getVCmpInst: return the vector compare instruction for the specified
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// vector type and condition code. Since this is for altivec specific code,
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// only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
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// only support the altivec types (v16i8, v8i16, v4i32, v2i64, v1i128,
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// and v4f32).
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static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
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bool HasVSX, bool &Swap, bool &Negate) {
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Swap = false;
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@ -4029,6 +4030,8 @@ static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
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return PPC::VCMPEQUW;
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else if (VecVT == MVT::v2i64)
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return PPC::VCMPEQUD;
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else if (VecVT == MVT::v1i128)
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return PPC::VCMPEQUQ;
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break;
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case ISD::SETGT:
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if (VecVT == MVT::v16i8)
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@ -4039,6 +4042,8 @@ static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
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return PPC::VCMPGTSW;
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else if (VecVT == MVT::v2i64)
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return PPC::VCMPGTSD;
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else if (VecVT == MVT::v1i128)
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return PPC::VCMPGTSQ;
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break;
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case ISD::SETUGT:
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if (VecVT == MVT::v16i8)
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@ -4049,6 +4054,8 @@ static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
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return PPC::VCMPGTUW;
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else if (VecVT == MVT::v2i64)
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return PPC::VCMPGTUD;
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else if (VecVT == MVT::v1i128)
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return PPC::VCMPGTUQ;
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break;
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default:
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break;
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@ -1005,7 +1005,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::SUB, MVT::v2i64, Expand);
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}
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setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
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if (Subtarget.isISA3_1())
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setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
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else
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setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
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setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
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AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
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@ -10212,6 +10215,26 @@ static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
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return false;
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break;
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case Intrinsic::ppc_altivec_vcmpequq:
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case Intrinsic::ppc_altivec_vcmpgtsq:
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case Intrinsic::ppc_altivec_vcmpgtuq:
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if (!Subtarget.isISA3_1())
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return false;
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switch (IntrinsicID) {
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default:
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llvm_unreachable("Unknown comparison intrinsic.");
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case Intrinsic::ppc_altivec_vcmpequq:
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CompareOpc = 455;
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break;
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case Intrinsic::ppc_altivec_vcmpgtsq:
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CompareOpc = 903;
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break;
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case Intrinsic::ppc_altivec_vcmpgtuq:
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CompareOpc = 647;
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break;
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}
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break;
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// VSX predicate comparisons use the same infrastructure
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case Intrinsic::ppc_vsx_xvcmpeqdp_p:
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case Intrinsic::ppc_vsx_xvcmpgedp_p:
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250
test/CodeGen/PowerPC/vec_cmpq.ll
Normal file
250
test/CodeGen/PowerPC/vec_cmpq.ll
Normal file
@ -0,0 +1,250 @@
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; Test the quadword comparison instructions that were added in POWER10.
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;
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 < %s | FileCheck %s
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define <1 x i128> @v1si128_cmp(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
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%cmp = icmp eq <1 x i128> %x, %y
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%result = sext <1 x i1> %cmp to <1 x i128>
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ret <1 x i128> %result
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; CHECK-LABEL: v1si128_cmp:
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; CHECK: vcmpequq 2, 2, 3
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}
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define <2 x i128> @v2si128_cmp(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
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%cmp = icmp eq <2 x i128> %x, %y
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%result = sext <2 x i1> %cmp to <2 x i128>
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ret <2 x i128> %result
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; CHECK-LABEL: v2si128_cmp
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <4 x i128> @v4si128_cmp(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
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%cmp = icmp eq <4 x i128> %x, %y
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%result = sext <4 x i1> %cmp to <4 x i128>
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ret <4 x i128> %result
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; CHECK-LABEL: v4si128_cmp
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <8 x i128> @v8si128_cmp(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
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%cmp = icmp eq <8 x i128> %x, %y
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%result = sext <8 x i1> %cmp to <8 x i128>
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ret <8 x i128> %result
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; CHECK-LABEL: v8si128_cmp
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <16 x i128> @v16si128_cmp(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
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%cmp = icmp eq <16 x i128> %x, %y
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%result = sext <16 x i1> %cmp to <16 x i128>
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ret <16 x i128> %result
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; CHECK-LABEL: v16si128_cmp
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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; Greater than signed
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define <1 x i128> @v1si128_cmp_gt(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
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%cmp = icmp sgt <1 x i128> %x, %y
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%result = sext <1 x i1> %cmp to <1 x i128>
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ret <1 x i128> %result
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; CHECK-LABEL: v1si128_cmp_gt
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <2 x i128> @v2si128_cmp_gt(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
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%cmp = icmp sgt <2 x i128> %x, %y
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%result = sext <2 x i1> %cmp to <2 x i128>
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ret <2 x i128> %result
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; CHECK-LABEL: v2si128_cmp_gt
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <4 x i128> @v4si128_cmp_gt(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
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%cmp = icmp sgt <4 x i128> %x, %y
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%result = sext <4 x i1> %cmp to <4 x i128>
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ret <4 x i128> %result
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; CHECK-LABEL: v4si128_cmp_gt
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <8 x i128> @v8si128_cmp_gt(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
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%cmp = icmp sgt <8 x i128> %x, %y
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%result = sext <8 x i1> %cmp to <8 x i128>
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ret <8 x i128> %result
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; CHECK-LABEL: v8si128_cmp_gt
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <16 x i128> @v16si128_cmp_gt(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
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%cmp = icmp sgt <16 x i128> %x, %y
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%result = sext <16 x i1> %cmp to <16 x i128>
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ret <16 x i128> %result
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; CHECK-LABEL: v16si128_cmp_gt
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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; Greater than unsigned
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define <1 x i128> @v1ui128_cmp_gt(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
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%cmp = icmp ugt <1 x i128> %x, %y
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%result = sext <1 x i1> %cmp to <1 x i128>
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ret <1 x i128> %result
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; CHECK-LABEL: v1ui128_cmp_gt
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <2 x i128> @v2ui128_cmp_gt(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
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%cmp = icmp ugt <2 x i128> %x, %y
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%result = sext <2 x i1> %cmp to <2 x i128>
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ret <2 x i128> %result
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; CHECK-LABEL: v2ui128_cmp_gt
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <4 x i128> @v4ui128_cmp_gt(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
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%cmp = icmp ugt <4 x i128> %x, %y
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%result = sext <4 x i1> %cmp to <4 x i128>
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ret <4 x i128> %result
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; CHECK-LABEL: v4ui128_cmp_gt
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <8 x i128> @v8ui128_cmp_gt(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
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%cmp = icmp ugt <8 x i128> %x, %y
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%result = sext <8 x i1> %cmp to <8 x i128>
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ret <8 x i128> %result
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; CHECK-LABEL: v8ui128_cmp_gt
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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}
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define <16 x i128> @v16ui128_cmp_gt(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
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%cmp = icmp ugt <16 x i128> %x, %y
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%result = sext <16 x i1> %cmp to <16 x i128>
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ret <16 x i128> %result
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; CHECK-LABEL: v16ui128_cmp_gt
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
; Check the intrinsics also
|
||||
declare <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>, <1 x i128>) nounwind readnone
|
||||
declare <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>, <1 x i128>) nounwind readnone
|
||||
declare <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>, <1 x i128>) nounwind readnone
|
||||
|
||||
define <1 x i128> @test_vcmpequq(<1 x i128> %x, <1 x i128> %y) {
|
||||
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> %x, <1 x i128> %y)
|
||||
ret <1 x i128> %tmp
|
||||
; CHECK-LABEL: test_vcmpequq:
|
||||
; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define <1 x i128> @test_vcmpgtsq(<1 x i128> %x, <1 x i128> %y) {
|
||||
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> %x, <1 x i128> %y)
|
||||
ret <1 x i128> %tmp
|
||||
; CHECK-LABEL: test_vcmpgtsq
|
||||
; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define <1 x i128> @test_vcmpgtuq(<1 x i128> %x, <1 x i128> %y) {
|
||||
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> %x, <1 x i128> %y)
|
||||
ret <1 x i128> %tmp
|
||||
; CHECK-LABEL: test_vcmpgtuq
|
||||
; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
|
||||
; CHECK: blr
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user