RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Code Issues Projects Releases Wiki Activity

[SystemZ] Bugfix in expandRxSBG()

Browse Source 
Csmith discovered a program that caused wrong code generation with -O0:

When handling a SIGN_EXTEND in expandRxSBG(), RxSBG.BitSize may be less than
the Input width (if a truncate was previously traversed), so maskMatters()
should be called with a masked based on the width of the sign extend result
instead.

Review: Ulrich Weigand
llvm-svn: 319892
This commit is contained in:
Jonas Paulsson 2017-12-06 13:53:24 +00:00
parent d1fdab7a0c
commit 3a2b48b970
2 changed files with 33 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -838,9 +838,16 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
case ISD::SIGN_EXTEND: {
// Check that the extension bits are don't-care (i.e. are masked out
// by the final mask).
unsigned BitSize = N.getValueSizeInBits();
unsigned InnerBitSize = N.getOperand(0).getValueSizeInBits();
if (maskMatters(RxSBG, allOnes(RxSBG.BitSize) - allOnes(InnerBitSize)))
return false;
if (maskMatters(RxSBG, allOnes(BitSize) - allOnes(InnerBitSize))) {
// In the case where only the sign bit is active, increase Rotate with
// the extension width.
if (RxSBG.Mask == 1 && RxSBG.Rotate == 1)
RxSBG.Rotate += (BitSize - InnerBitSize);
else
return false;
}
RxSBG.Input = N.getOperand(0);
return true;

24
test/CodeGen/SystemZ/rosbg-02.ll Normal file
View File

@ -0,0 +1,24 @@
; Test that a rosbg conversion involving a sign extend operation rotates with
; the right number of steps.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 | FileCheck %s
@g_136 = external global i16, align 2
@g_999 = external global i32, align 4
; Function Attrs: nounwind
define void @main() {
%1 = load i32, i32* undef, align 4
store i16 -28141, i16* @g_136, align 2
%2 = load i32, i32* undef, align 4
%3 = xor i32 -28141, %2
%4 = xor i32 %1, %3
%5 = sext i32 %4 to i64
%6 = icmp sgt i64 0, %5
%7 = zext i1 %6 to i32
%8 = load i32, i32* @g_999, align 4
%9 = or i32 %8, %7
; CHECK: rosbg %r1, %r3, 63, 63, 33
store i32 %9, i32* @g_999, align 4
ret void
}