From 3a37dfb0762c2316140ec67a0bfdf511ae6f309d Mon Sep 17 00:00:00 2001
From: Fraser Cormack <fraser@codeplay.com>
Date: Wed, 31 Mar 2021 12:59:22 +0100
Subject: [PATCH] [RISCV] Test llvm.experimental.vector.insert intrinsics on
 RV32

RV32 is able to use the llvm.experimental.vector.insert intrinsics too.
This patch ensures they're tested.

Reviewed By: khchen, asb

Differential Revision: https://reviews.llvm.org/D99655
---
 test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll | 2 ++
 test/CodeGen/RISCV/rvv/insert-subvector.ll               | 1 +
 2 files changed, 3 insertions(+)

diff --git a/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
index 194fe3400e6..7978fb773c5 100644
--- a/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
+++ b/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
@@ -1,4 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
+; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
diff --git a/test/CodeGen/RISCV/rvv/insert-subvector.ll b/test/CodeGen/RISCV/rvv/insert-subvector.ll
index e1e46fb6610..3fa3ec19ecd 100644
--- a/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -1,4 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s | FileCheck %s
 
 define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {