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Fold X+Y -> X|Y when safe. This implements:

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Regression/CodeGen/PowerPC/and_add.ll

a case that occurs with dynamic allocas of constant size.

llvm-svn: 26727
This commit is contained in:
Chris Lattner 2006-03-13 06:51:27 +00:00
parent 7821da357e
commit 3a3c8682b5
1 changed files with 19 additions and 1 deletions
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20
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -714,9 +714,27 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
// fold (A+(B-A)) -> B
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
return N1.getOperand(0);
//
if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand();
// fold (a+b) -> (a|b) iff a and b share no bits.
if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
uint64_t LHSZero, LHSOne;
uint64_t RHSZero, RHSOne;
uint64_t Mask = MVT::getIntVTBitMask(VT);
TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
if (LHSZero) {
TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
return DAG.getNode(ISD::OR, VT, N0, N1);
}
}
return SDOperand();
}