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Add instruction encodings / disassembly support 3r instructions.

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It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
This commit is contained in:
Richard Osborne 2013-01-20 17:18:47 +00:00
parent 61727f1583
commit 3a5e1fcceb
4 changed files with 205 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

150
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -132,6 +132,11 @@ static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus Decode3RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
#include "XCoreGenDisassemblerTables.inc" #include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@ -159,11 +164,15 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
static DecodeStatus static DecodeStatus
Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
unsigned Combined = fieldFromInstruction(Insn, 6, 5) + unsigned Combined = fieldFromInstruction(Insn, 6, 5);
fieldFromInstruction(Insn, 5, 1) * 5 - 27; if (Combined < 27)
if (Combined >= 9)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (fieldFromInstruction(Insn, 5, 1)) {
if (Combined == 31)
return MCDisassembler::Fail;
Combined += 5;
}
Combined -= 27;
unsigned Op1High = Combined % 3; unsigned Op1High = Combined % 3;
unsigned Op2High = Combined / 3; unsigned Op2High = Combined / 3;
Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
@ -171,15 +180,78 @@ Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus
Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
unsigned &Op3) {
unsigned Combined = fieldFromInstruction(Insn, 6, 5);
if (Combined >= 27)
return MCDisassembler::Fail;
unsigned Op1High = Combined % 3;
unsigned Op2High = (Combined / 3) % 3;
unsigned Op3High = Combined / 9;
Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
return MCDisassembler::Success;
}
static DecodeStatus
Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a 3R instruction.
unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
switch (Opcode) {
case 0x2:
Inst.setOpcode(XCore::ADD_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x3:
Inst.setOpcode(XCore::SUB_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x4:
Inst.setOpcode(XCore::SHL_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x5:
Inst.setOpcode(XCore::SHR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x6:
Inst.setOpcode(XCore::EQ_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x7:
Inst.setOpcode(XCore::AND_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x8:
Inst.setOpcode(XCore::OR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x9:
Inst.setOpcode(XCore::LDW_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x10:
Inst.setOpcode(XCore::LD16S_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x11:
Inst.setOpcode(XCore::LD8U_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x18:
Inst.setOpcode(XCore::LSS_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x19:
Inst.setOpcode(XCore::LSU_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
static DecodeStatus static DecodeStatus
Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
} DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
@ -188,10 +260,11 @@ DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
} DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
@ -200,11 +273,12 @@ Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
} DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
@ -213,10 +287,11 @@ DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op2));
} DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op2));
return S; return S;
} }
@ -225,10 +300,11 @@ DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
} DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S; return S;
} }
@ -237,11 +313,12 @@ DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) { if (S != MCDisassembler::Success)
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
} DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S; return S;
} }
@ -271,6 +348,19 @@ DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S; return S;
} }
static DecodeStatus
Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
MCDisassembler::DecodeStatus MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr, XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size, uint64_t &Size,

4
lib/Target/XCore/XCoreInstrFormats.td
View File

@ -33,8 +33,10 @@ class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
// Instruction formats // Instruction formats
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class _F3R<dag outs, dag ins, string asmstr, list<dag> pattern> class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> { : InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc;
let DecoderMethod = "Decode3RInstruction";
} }
class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern> class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>

98
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -200,48 +200,40 @@ def InlineJT32 : Operand<i32> {
// Three operand short // Three operand short
multiclass F3R_2RUS<string OpcStr, SDNode OpNode> { multiclass F3R_2RUS<bits<5> opc, string OpcStr, SDNode OpNode> {
def _3r: _F3R< def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), !strconcat(OpcStr, " $dst, $b, $c"),
!strconcat(OpcStr, " $dst, $b, $c"), [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
def _2rus : _F2RUS< !strconcat(OpcStr, " $dst, $b, $c"),
(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
!strconcat(OpcStr, " $dst, $b, $c"),
[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
} }
multiclass F3R_2RUS_np<string OpcStr> { multiclass F3R_2RUS_np<bits<5> opc, string OpcStr> {
def _3r: _F3R< def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), !strconcat(OpcStr, " $dst, $b, $c"), []>;
!strconcat(OpcStr, " $dst, $b, $c"), def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
[]>; !strconcat(OpcStr, " $dst, $b, $c"), []>;
def _2rus : _F2RUS<
(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
!strconcat(OpcStr, " $dst, $b, $c"),
[]>;
} }
multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> { multiclass F3R_2RBITP<bits<5> opc, string OpcStr, SDNode OpNode> {
def _3r: _F3R< def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), !strconcat(OpcStr, " $dst, $b, $c"),
!strconcat(OpcStr, " $dst, $b, $c"), [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
def _2rus : _F2RUS< def _2rus : _F2RUS<
(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
!strconcat(OpcStr, " $dst, $b, $c"), !strconcat(OpcStr, " $dst, $b, $c"),
[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
} }
class F3R<string OpcStr, SDNode OpNode> : _F3R< class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
!strconcat(OpcStr, " $dst, $b, $c"), !strconcat(OpcStr, " $dst, $b, $c"),
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
class F3R_np<string OpcStr> : _F3R< class F3R_np<bits<5> opc, string OpcStr> :
(outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
!strconcat(OpcStr, " $dst, $b, $c"), !strconcat(OpcStr, " $dst, $b, $c"), []>;
[]>;
// Three operand long // Three operand long
/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
@ -390,46 +382,44 @@ let usesCustomInserter = 1 in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Three operand short // Three operand short
defm ADD : F3R_2RUS<"add", add>; defm ADD : F3R_2RUS<0b00010, "add", add>;
defm SUB : F3R_2RUS<"sub", sub>; defm SUB : F3R_2RUS<0b00011, "sub", sub>;
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
defm EQ : F3R_2RUS_np<"eq">; defm EQ : F3R_2RUS_np<0b00110, "eq">;
def LSS_3r : F3R_np<"lss">; def LSS_3r : F3R_np<0b11000, "lss">;
def LSU_3r : F3R_np<"lsu">; def LSU_3r : F3R_np<0b11001, "lsu">;
} }
def AND_3r : F3R<"and", and>; def AND_3r : F3R<0b00111, "and", and>;
def OR_3r : F3R<"or", or>; def OR_3r : F3R<0b01000, "or", or>;
let mayLoad=1 in { let mayLoad=1 in {
def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
"ldw $dst, $addr[$offset]", (ins GRRegs:$addr, GRRegs:$offset),
[]>; "ldw $dst, $addr[$offset]", []>;
def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
"ldw $dst, $addr[$offset]", "ldw $dst, $addr[$offset]",
[]>; []>;
def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
"ld16s $dst, $addr[$offset]", (ins GRRegs:$addr, GRRegs:$offset),
[]>; "ld16s $dst, $addr[$offset]", []>;
def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
"ld8u $dst, $addr[$offset]", (ins GRRegs:$addr, GRRegs:$offset),
[]>; "ld8u $dst, $addr[$offset]", []>;
} }
let mayStore=1 in { let mayStore=1 in {
def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
"stw $val, $addr[$offset]", "stw $val, $addr[$offset]", []>;
[]>;
def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
"stw $val, $addr[$offset]", "stw $val, $addr[$offset]", []>;
[]>;
} }
defm SHL : F3R_2RBITP<"shl", shl>; defm SHL : F3R_2RBITP<0b00100, "shl", shl>;
defm SHR : F3R_2RBITP<"shr", srl>; defm SHR : F3R_2RBITP<0b00101, "shr", srl>;
// TODO tsetr // TODO tsetr
// Three operand long // Three operand long

38
test/MC/Disassembler/XCore/xcore.txt
View File

@ -196,3 +196,41 @@
# CHECK: settw res[r7], r2 # CHECK: settw res[r7], r2
0x9b 0xff 0xec 0x27 0x9b 0xff 0xec 0x27
# 3r instructions
# CHECK: add r1, r2, r3
0x1b 0x10
# CHECK: and r11, r10, r9
0xb9 0x3e
# CHECK: eq r6, r1, r2
0x66 0x30
# CHECK: ld16s r8, r3[r4]
0xcc 0x82
# CHECK: ld8u r9, r1[r10]
0x16 0x8d
# CHECK: ldw r9, r4[r5]
0x91 0x4b
# CHECK: lss r7, r3, r0
0x7c 0xc0
# CHECK: lsu r5, r8, r6
0x12 0xcc
# CHECK: or r1, r3, r2
0x1e 0x40
# CHECK: shl r8, r2, r4
0xc8 0x22
# CHECK: shr r9, r7, r1
0x5d 0x29
# CHECK: sub r4, r2, r5
0x89 0x1a