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[SelDag] Add isIntOrFPConstant helper function.

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This patch adds a new isIntOrFPConstant  helper function to check if a
SDValue is a integer of FP constant. This pattern is used in various
places.

There also are places that incorrectly just check for integer constants,
e.g. D99384, so hopefully this helper will help people avoid that issue.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D99428
This commit is contained in:
Florian Hahn 2021-03-28 12:48:58 +01:00
parent 3039a6f04c
commit 3a9af0ee66
3 changed files with 12 additions and 7 deletions
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5
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -1684,6 +1684,11 @@ bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false);
/// Does not permit build vector implicit truncation.
bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false);
/// Return true if \p V is either a integer or FP constant.
inline bool isIntOrFPConstant(SDValue V) {
return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V);
}
class GlobalAddressSDNode : public SDNode {
friend class SelectionDAG;

8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -12413,7 +12413,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
VT.getVectorElementType());
// If the input is a constant, let getNode fold it.
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
if (isIntOrFPConstant(N0)) {
// If we can't allow illegal operations, we need to check that this is just
// a fp -> int or int -> conversion and that the resulting operation will
// be legal.
@ -12651,7 +12651,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
return N0;
// If the input is a constant, return it.
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0))
if (isIntOrFPConstant(N0))
return N0;
return SDValue();
@ -16912,7 +16912,7 @@ void DAGCombiner::getStoreMergeCandidates(
case StoreSource::Constant:
if (NoTypeMatch)
return false;
if (!(isa<ConstantSDNode>(OtherBC) || isa<ConstantFPSDNode>(OtherBC)))
if (!isIntOrFPConstant(OtherBC))
return false;
break;
case StoreSource::Extract:
@ -20492,7 +20492,7 @@ static SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN,
// generating a splat; semantically, this is fine, but it's likely to
// generate low-quality code if the target can't reconstruct an appropriate
// shuffle.
if (!Op.isUndef() && !isa<ConstantSDNode>(Op) && !isa<ConstantFPSDNode>(Op))
if (!Op.isUndef() && !isIntOrFPConstant(Op))
if (!IsSplat && !DuplicateOps.insert(Op).second)
return SDValue();

6
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -9680,10 +9680,10 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
}
if (i > 0)
isOnlyLowElement = false;
if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
if (!isIntOrFPConstant(V))
isConstant = false;
if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
if (isIntOrFPConstant(V)) {
++NumConstantLanes;
if (!ConstantValue.getNode())
ConstantValue = V;
@ -9849,7 +9849,7 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
for (unsigned i = 0; i < NumElts; ++i) {
SDValue V = Op.getOperand(i);
SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V))
if (!isIntOrFPConstant(V))
// Note that type legalization likely mucked about with the VT of the
// source operand, so we may have to convert it here before inserting.
Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);