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[X86][BtVer2] Cleanup some old FIXMEs from the model. NFCI.

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llvm-svn: 330428
This commit is contained in:
Simon Pilgrim 2018-04-20 13:12:04 +00:00
parent 404cf2b1bb
commit 3aaec060ee
1 changed files with 2 additions and 5 deletions
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7
lib/Target/X86/X86ScheduleBtVer2.td
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@ -278,15 +278,13 @@ defm : JWriteResIntPair<WriteJump, [JALU01], 1>;
def : WriteRes<WriteSystem, [JALU01]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [JALU01]> { let Latency = 100; }
def : WriteRes<WriteFence, [JSAGU]>;
// Nops don't have dependencies, so there's no actual latency, but we set this
// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
////////////////////////////////////////////////////////////////////////////////
// Floating point. This covers both scalar and vector operations.
// FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
// FIXME: Double precision latencies
// FIXME: SS vs PS latencies
////////////////////////////////////////////////////////////////////////////////
def : WriteRes<WriteFLoad, [JLAGU, JFPU01, JFPX]> { let Latency = 5; }
@ -311,7 +309,6 @@ defm : JWriteResFpuPair<WriteFVarShuffle256, [JFPU01, JFPX], 1>; // NOTE: Doesn
////////////////////////////////////////////////////////////////////////////////
// Conversions.
// FIXME: integer pipes
////////////////////////////////////////////////////////////////////////////////
defm : JWriteResFpuPair<WriteCvtF2I, [JFPU1, JSTC], 3>; // Float -> Integer.
@ -344,7 +341,7 @@ def JWriteCVTF2SILd : SchedWriteRes<[JLAGU, JFPU1, JSTC, JFPA, JALU0]> {
}
def : InstRW<[JWriteCVTF2SILd], (instregex "(V)?CVT(T?)S(D|S)2SI(64)?rm")>;
// FIXME: f+3 ST,LD+STC latency
// FIXME: f+3 ST, LD+STC latency
def JWriteCVTSI2F : SchedWriteRes<[JFPU1, JSTC]> {
let Latency = 9;
let NumMicroOps = 2;