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Fix comments.
llvm-svn: 41947
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@ -157,8 +157,8 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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.addReg(PPC::R0, false, false, true), FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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// R0 = ADDI FI#
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// STVX VAL, 0, R0
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
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@ -210,8 +210,8 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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// R0 = ADDI FI#
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// Dest = LVX 0, R0
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
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