From 3abaabacbe250bedfdb20f1a23173b23b0ca0953 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 19 Jan 2017 03:49:29 +0000 Subject: [PATCH] [X86] Merge LowerADD and LowerSUB into a single LowerADD_SUB since they are identical. llvm-svn: 292469 --- lib/Target/X86/X86ISelLowering.cpp | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index b686c42b3f1..e5c5975b757 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -20846,17 +20846,7 @@ static SDValue Lower512IntArith(SDValue Op, SelectionDAG &DAG) { DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); } -static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) { - if (Op.getValueType() == MVT::i1) - return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(), - Op.getOperand(0), Op.getOperand(1)); - assert(Op.getSimpleValueType().is256BitVector() && - Op.getSimpleValueType().isInteger() && - "Only handle AVX 256-bit vector integer operation"); - return Lower256IntArith(Op, DAG); -} - -static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) { +static SDValue LowerADD_SUB(SDValue Op, SelectionDAG &DAG) { if (Op.getValueType() == MVT::i1) return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(), Op.getOperand(0), Op.getOperand(1)); @@ -23404,8 +23394,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::ADDE: case ISD::SUBC: case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); - case ISD::ADD: return LowerADD(Op, DAG); - case ISD::SUB: return LowerSUB(Op, DAG); + case ISD::ADD: + case ISD::SUB: return LowerADD_SUB(Op, DAG); case ISD::SMAX: case ISD::SMIN: case ISD::UMAX: