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Allows instructions which no explicit operands. e.g. X86 RET which has but

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an implicit flag operand.

llvm-svn: 24916
This commit is contained in:
Evan Cheng 2005-12-21 20:20:49 +00:00
parent dfc6bbd0d4
commit 3b09247bb9
1 changed files with 5 additions and 6 deletions
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11
utils/TableGen/DAGISelEmitter.cpp
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@ -1124,23 +1124,22 @@ void DAGISelEmitter::ParseInstructions() {
std::vector<Record*> Operands;
CodeGenInstruction &InstInfo =Target.getInstruction(Instrs[i]->getName());
// Doesn't even define a result?
if (InstInfo.OperandList.size() == 0)
continue;
// Note: Removed if (InstInfo.OperandList.size() == 0) continue;
// It's possible for some instruction, e.g. RET for X86 that only has an
// implicit flag operand.
// FIXME: temporary hack...
if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
InstInfo.isStore) {
// These produce no results
for (unsigned j = 0, e = InstInfo.OperandList.size(); j != e; ++j)
for (unsigned j = 0, e = InstInfo.OperandList.size(); j < e; ++j)
Operands.push_back(InstInfo.OperandList[j].Rec);
} else {
// Assume the first operand is the result.
Results.push_back(InstInfo.OperandList[0].Rec);
// The rest are inputs.
for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
for (unsigned j = 1, e = InstInfo.OperandList.size(); j < e; ++j)
Operands.push_back(InstInfo.OperandList[j].Rec);
}