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64-bit atomic instructions.
llvm-svn: 144372
This commit is contained in:
Akira Hatanaka
parent
40d8c440ad
commit
3b1457c21d
@ -81,6 +81,28 @@ class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
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class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
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Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
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multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
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def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>;
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def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]>;
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}
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multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
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def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>;
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def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
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Requires<[IsN64]>;
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}
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let usesCustomInserter = 1, Predicates = [HasMips64] in {
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defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
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defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
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defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">;
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defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">;
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defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">;
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defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">;
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defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">;
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defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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@ -146,6 +168,12 @@ defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
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defm ULD : LoadM64<0x37, "uld", load_u, 1>;
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defm USD : StoreM64<0x3f, "usd", store_u, 1>;
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/// Load-linked, Store-conditional
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def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>;
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def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]>;
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def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>;
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def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
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/// Jump and Branch Instructions
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def JAL64 : JumpLink64<0x03, "jal">;
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def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">;
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@ -794,60 +794,108 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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assert(false && "Unexpected instr type to insert");
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return NULL;
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case Mips::ATOMIC_LOAD_ADD_I8:
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case Mips::ATOMIC_LOAD_ADD_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
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case Mips::ATOMIC_LOAD_ADD_I16:
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case Mips::ATOMIC_LOAD_ADD_I16_P8:
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return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
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case Mips::ATOMIC_LOAD_ADD_I32:
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case Mips::ATOMIC_LOAD_ADD_I32_P8:
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return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
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case Mips::ATOMIC_LOAD_ADD_I64:
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case Mips::ATOMIC_LOAD_ADD_I64_P8:
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return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
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case Mips::ATOMIC_LOAD_AND_I8:
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case Mips::ATOMIC_LOAD_AND_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
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case Mips::ATOMIC_LOAD_AND_I16:
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case Mips::ATOMIC_LOAD_AND_I16_P8:
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return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
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case Mips::ATOMIC_LOAD_AND_I32:
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case Mips::ATOMIC_LOAD_AND_I32_P8:
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return EmitAtomicBinary(MI, BB, 4, Mips::AND);
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case Mips::ATOMIC_LOAD_AND_I64:
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case Mips::ATOMIC_LOAD_AND_I64_P8:
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return EmitAtomicBinary(MI, BB, 48, Mips::AND64);
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case Mips::ATOMIC_LOAD_OR_I8:
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case Mips::ATOMIC_LOAD_OR_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
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case Mips::ATOMIC_LOAD_OR_I16:
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case Mips::ATOMIC_LOAD_OR_I16_P8:
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return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
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case Mips::ATOMIC_LOAD_OR_I32:
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case Mips::ATOMIC_LOAD_OR_I32_P8:
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return EmitAtomicBinary(MI, BB, 4, Mips::OR);
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case Mips::ATOMIC_LOAD_OR_I64:
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case Mips::ATOMIC_LOAD_OR_I64_P8:
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return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
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case Mips::ATOMIC_LOAD_XOR_I8:
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case Mips::ATOMIC_LOAD_XOR_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
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case Mips::ATOMIC_LOAD_XOR_I16:
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case Mips::ATOMIC_LOAD_XOR_I16_P8:
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return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
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case Mips::ATOMIC_LOAD_XOR_I32:
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case Mips::ATOMIC_LOAD_XOR_I32_P8:
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return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
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case Mips::ATOMIC_LOAD_XOR_I64:
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case Mips::ATOMIC_LOAD_XOR_I64_P8:
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return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
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case Mips::ATOMIC_LOAD_NAND_I8:
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case Mips::ATOMIC_LOAD_NAND_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
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case Mips::ATOMIC_LOAD_NAND_I16:
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case Mips::ATOMIC_LOAD_NAND_I16_P8:
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return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
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case Mips::ATOMIC_LOAD_NAND_I32:
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case Mips::ATOMIC_LOAD_NAND_I32_P8:
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return EmitAtomicBinary(MI, BB, 4, 0, true);
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case Mips::ATOMIC_LOAD_NAND_I64:
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case Mips::ATOMIC_LOAD_NAND_I64_P8:
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return EmitAtomicBinary(MI, BB, 8, 0, true);
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case Mips::ATOMIC_LOAD_SUB_I8:
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case Mips::ATOMIC_LOAD_SUB_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
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case Mips::ATOMIC_LOAD_SUB_I16:
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case Mips::ATOMIC_LOAD_SUB_I16_P8:
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return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
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case Mips::ATOMIC_LOAD_SUB_I32:
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case Mips::ATOMIC_LOAD_SUB_I32_P8:
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return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
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case Mips::ATOMIC_LOAD_SUB_I64:
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case Mips::ATOMIC_LOAD_SUB_I64_P8:
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return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
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case Mips::ATOMIC_SWAP_I8:
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case Mips::ATOMIC_SWAP_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, 0);
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case Mips::ATOMIC_SWAP_I16:
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case Mips::ATOMIC_SWAP_I16_P8:
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return EmitAtomicBinaryPartword(MI, BB, 2, 0);
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case Mips::ATOMIC_SWAP_I32:
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case Mips::ATOMIC_SWAP_I32_P8:
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return EmitAtomicBinary(MI, BB, 4, 0);
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case Mips::ATOMIC_SWAP_I64:
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case Mips::ATOMIC_SWAP_I64_P8:
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return EmitAtomicBinary(MI, BB, 8, 0);
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case Mips::ATOMIC_CMP_SWAP_I8:
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case Mips::ATOMIC_CMP_SWAP_I8_P8:
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return EmitAtomicCmpSwapPartword(MI, BB, 1);
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case Mips::ATOMIC_CMP_SWAP_I16:
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case Mips::ATOMIC_CMP_SWAP_I16_P8:
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return EmitAtomicCmpSwapPartword(MI, BB, 2);
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case Mips::ATOMIC_CMP_SWAP_I32:
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case Mips::ATOMIC_CMP_SWAP_I32_P8:
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return EmitAtomicCmpSwap(MI, BB, 4);
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case Mips::ATOMIC_CMP_SWAP_I64:
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case Mips::ATOMIC_CMP_SWAP_I64_P8:
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return EmitAtomicCmpSwap(MI, BB, 8);
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}
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}
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@ -857,13 +905,31 @@ MachineBasicBlock *
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MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size, unsigned BinOpcode,
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bool Nand) const {
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assert(Size == 4 && "Unsupported size for EmitAtomicBinary.");
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assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
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const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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unsigned LL, SC, AND, NOR, ZERO, BEQ;
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if (Size == 4) {
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LL = IsN64 ? Mips::LL_P8 : Mips::LL;
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SC = IsN64 ? Mips::SC_P8 : Mips::SC;
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AND = Mips::AND;
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NOR = Mips::NOR;
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ZERO = Mips::ZERO;
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BEQ = Mips::BEQ;
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}
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else {
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LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
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SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
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AND = Mips::AND64;
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NOR = Mips::NOR64;
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ZERO = Mips::ZERO_64;
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BEQ = Mips::BEQ64;
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}
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unsigned OldVal = MI->getOperand(0).getReg();
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unsigned Ptr = MI->getOperand(1).getReg();
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@ -901,23 +967,20 @@ MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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// sc success, storeval, 0(ptr)
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// beq success, $0, loopMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
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if (Nand) {
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// and andres, oldval, incr
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// nor storeval, $0, andres
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BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr);
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BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal)
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.addReg(Mips::ZERO).addReg(AndRes);
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BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
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BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
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} else if (BinOpcode) {
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// <binop> storeval, oldval, incr
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BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
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} else {
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StoreVal = Incr;
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}
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BuildMI(BB, dl, TII->get(Mips::SC), Success)
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.addReg(StoreVal).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
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BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
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MI->eraseFromParent(); // The instruction is gone now.
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@ -937,6 +1000,8 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
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unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Ptr = MI->getOperand(1).getReg();
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@ -1028,7 +1093,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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// beq success,$0,loopMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
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BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
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if (Nand) {
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// and andres, oldval, incr2
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// nor binopres, $0, andres
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@ -1051,7 +1116,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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.addReg(OldVal).addReg(Mask2);
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BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
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.addReg(MaskedOldVal0).addReg(NewVal);
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BuildMI(BB, dl, TII->get(Mips::SC), Success)
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BuildMI(BB, dl, TII->get(SC), Success)
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.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
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@ -1082,13 +1147,29 @@ MachineBasicBlock *
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MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size) const {
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assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap.");
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assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
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const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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unsigned LL, SC, ZERO, BNE, BEQ;
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if (Size == 4) {
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LL = IsN64 ? Mips::LL_P8 : Mips::LL;
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SC = IsN64 ? Mips::SC_P8 : Mips::SC;
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ZERO = Mips::ZERO;
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BNE = Mips::BNE;
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BEQ = Mips::BEQ;
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}
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else {
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LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
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SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
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ZERO = Mips::ZERO_64;
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BNE = Mips::BNE64;
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BEQ = Mips::BEQ64;
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}
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Ptr = MI->getOperand(1).getReg();
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@ -1127,18 +1208,18 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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// ll dest, 0(ptr)
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// bne dest, oldval, exitMBB
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BB = loop1MBB;
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BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BNE))
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BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(BNE))
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.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
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// loop2MBB:
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// sc success, newval, 0(ptr)
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// beq success, $0, loop1MBB
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BB = loop2MBB;
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BuildMI(BB, dl, TII->get(Mips::SC), Success)
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BuildMI(BB, dl, TII->get(SC), Success)
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.addReg(NewVal).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
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BuildMI(BB, dl, TII->get(BEQ))
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.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
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MI->eraseFromParent(); // The instruction is gone now.
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@ -1157,6 +1238,8 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
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unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Ptr = MI->getOperand(1).getReg();
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@ -1247,7 +1330,7 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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// and maskedoldval0,oldval,mask
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// bne maskedoldval0,shiftedcmpval,sinkMBB
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BB = loop1MBB;
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BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
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BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
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.addReg(OldVal).addReg(Mask);
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BuildMI(BB, dl, TII->get(Mips::BNE))
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@ -1263,7 +1346,7 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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.addReg(OldVal).addReg(Mask2);
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BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
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.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
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BuildMI(BB, dl, TII->get(Mips::SC), Success)
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BuildMI(BB, dl, TII->get(SC), Success)
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.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
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@ -594,20 +594,41 @@ class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
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}
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// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
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class Atomic2Ops<PatFrag Op, string Opstr> :
|
||||
MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
|
||||
class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
|
||||
RegisterClass PRC> :
|
||||
MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
|
||||
!strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
|
||||
[(set CPURegs:$dst,
|
||||
(Op CPURegs:$ptr, CPURegs:$incr))]>;
|
||||
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
|
||||
|
||||
multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
|
||||
def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, Requires<[NotN64]>;
|
||||
def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]>;
|
||||
}
|
||||
|
||||
// Atomic Compare & Swap.
|
||||
class AtomicCmpSwap<PatFrag Op, string Width> :
|
||||
MipsPseudo<(outs CPURegs:$dst),
|
||||
(ins CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap),
|
||||
!strconcat("atomic_cmp_swap_", Width,
|
||||
"\t$dst, $ptr, $cmp, $swap"),
|
||||
[(set CPURegs:$dst,
|
||||
(Op CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap))]>;
|
||||
class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
|
||||
RegisterClass PRC> :
|
||||
MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
|
||||
!strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
|
||||
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
|
||||
|
||||
multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
|
||||
def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, Requires<[NotN64]>;
|
||||
def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]>;
|
||||
}
|
||||
|
||||
class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
|
||||
FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
|
||||
!strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
|
||||
FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
|
||||
!strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
|
||||
let mayStore = 1;
|
||||
let Constraints = "$rt = $dst";
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pseudo instructions
|
||||
@ -643,32 +664,32 @@ def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
|
||||
def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
|
||||
|
||||
let usesCustomInserter = 1 in {
|
||||
def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, "load_add_8">;
|
||||
def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, "load_add_16">;
|
||||
def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, "load_add_32">;
|
||||
def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, "load_sub_8">;
|
||||
def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, "load_sub_16">;
|
||||
def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, "load_sub_32">;
|
||||
def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, "load_and_8">;
|
||||
def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, "load_and_16">;
|
||||
def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, "load_and_32">;
|
||||
def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, "load_or_8">;
|
||||
def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, "load_or_16">;
|
||||
def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, "load_or_32">;
|
||||
def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, "load_xor_8">;
|
||||
def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, "load_xor_16">;
|
||||
def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, "load_xor_32">;
|
||||
def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, "load_nand_8">;
|
||||
def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, "load_nand_16">;
|
||||
def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, "load_nand_32">;
|
||||
defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
|
||||
defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
|
||||
defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
|
||||
defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
|
||||
defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
|
||||
defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
|
||||
defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
|
||||
defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
|
||||
defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
|
||||
defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
|
||||
defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
|
||||
defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
|
||||
defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
|
||||
defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
|
||||
defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
|
||||
defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
|
||||
defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
|
||||
defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
|
||||
|
||||
def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, "swap_8">;
|
||||
def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, "swap_16">;
|
||||
def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, "swap_32">;
|
||||
defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
|
||||
defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
|
||||
defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
|
||||
|
||||
def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, "8">;
|
||||
def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, "16">;
|
||||
def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, "32">;
|
||||
defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
|
||||
defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
|
||||
defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -745,12 +766,10 @@ def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
|
||||
}
|
||||
|
||||
/// Load-linked, Store-conditional
|
||||
let mayLoad = 1 in
|
||||
def LL : FMem<0x30, (outs CPURegs:$rt), (ins mem:$addr),
|
||||
"ll\t$rt, $addr", [], IILoad>;
|
||||
let mayStore = 1, Constraints = "$rt = $dst" in
|
||||
def SC : FMem<0x38, (outs CPURegs:$dst), (ins CPURegs:$rt, mem:$addr),
|
||||
"sc\t$rt, $addr", [], IIStore>;
|
||||
def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
|
||||
def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]>;
|
||||
def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
|
||||
def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
|
||||
|
||||
/// Jump and Branch Instructions
|
||||
def J : JumpFJ<0x02, "j">;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user