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https://github.com/RPCS3/llvm-mirror.git
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Next round of PPC CR optimizations. For the following code:
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
llvm-svn: 21321
This commit is contained in:
Nate Begeman
parent
4d9c1d06da
commit
3b1c0df702
@ -524,9 +524,11 @@ public:
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unsigned getGlobalBaseReg();
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unsigned getConstDouble(double floatVal, unsigned Result);
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void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
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bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
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unsigned FoldIfWideZeroExtend(SDOperand N);
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unsigned SelectCC(SDOperand CC, unsigned &Opc);
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unsigned SelectCC(SDOperand CC, unsigned &Opc, bool &Inv, unsigned &Idx);
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unsigned SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, unsigned &Idx);
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unsigned SelectExpr(SDOperand N, bool Recording=false);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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void Select(SDOperand N);
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@ -727,22 +729,6 @@ static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
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return 0;
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}
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/// getCRIdxForBCC - Return the index of the condition register field
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/// associated with the PowerPC branch instruction, and whether or not the field
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/// is treated as inverted. That is, lt = 0; ge = 0 inverted.
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static unsigned getCRIdxForBCC(unsigned Condition, bool& Inv) {
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switch (Condition) {
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default: assert(0 && "Unknown condition!"); abort();
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case PPC::BLT: Inv = false; return 29; // 28 -> 31, rol 29
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case PPC::BGE: Inv = true; return 29; // 28 -> 31, rol 29
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case PPC::BGT: Inv = false; return 30; // 29 -> 31, rol 30
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case PPC::BLE: Inv = true; return 30; // 29 -> 31, rol 30
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case PPC::BEQ: Inv = false; return 31; // 30 -> 31, rol 31
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case PPC::BNE: Inv = true; return 31; // 30 -> 31, rol 31
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}
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return 0;
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}
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/// IndexedOpForOp - Return the indexed variant for each of the PowerPC load
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/// and store immediate instructions.
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static unsigned IndexedOpForOp(unsigned Opcode) {
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@ -934,6 +920,23 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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return Result;
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}
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/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
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/// Inv is true, then invert the result.
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void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
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unsigned IntCR = MakeReg(MVT::i32);
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BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
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BuildMI(BB, PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
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if (Inv) {
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unsigned Tmp1 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
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.addImm(31).addImm(31);
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BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(1);
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} else {
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(IntCR).addImm(32-(3-Idx))
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.addImm(31).addImm(31);
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}
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}
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/// SelectBitfieldInsert - turn an or of two masked values into
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/// the rotate left word immediate then mask insert (rlwimi) instruction.
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/// Returns true on success, false if the caller still needs to select OR.
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@ -1033,7 +1036,7 @@ unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
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return SelectExpr(N);
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}
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unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) {
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unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
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unsigned Result, Tmp1, Tmp2;
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bool AlreadySelected = false;
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static const unsigned CompareOpcodes[] =
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@ -1047,6 +1050,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) {
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if (SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val)) {
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bool U;
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Opc = getBCCForSetCC(SetCC->getCondition(), U);
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Idx = getCRIdxForSetCC(SetCC->getCondition(), Inv);
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// Pass the optional argument U to getImmediateForOpcode for SETCC,
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// so that it knows whether the SETCC immediate range is signed or not.
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@ -1083,38 +1087,58 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) {
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}
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} else {
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if (PPCCRopts)
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if (CC.getOpcode() == ISD::AND || CC.getOpcode() == ISD::OR)
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if (CC.getOperand(0).Val->hasOneUse() &&
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CC.getOperand(1).Val->hasOneUse()) {
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SetCCSDNode* Op0CC = dyn_cast<SetCCSDNode>(CC.getOperand(0).Val);
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SetCCSDNode* Op1CC = dyn_cast<SetCCSDNode>(CC.getOperand(1).Val);
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if (Op0CC && Op1CC) {
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++MultiBranch;
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bool Inv0, Inv1;
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unsigned Opc1;
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unsigned Idx0 = getCRIdxForSetCC(Op0CC->getCondition(), Inv0);
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unsigned Idx1 = getCRIdxForSetCC(Op1CC->getCondition(), Inv1);
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unsigned CROpc = getCROpForSetCC(CC.getOpcode(), Inv0, Inv1);
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Tmp1 = SelectCC(CC.getOperand(0), Opc);
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Tmp2 = SelectCC(CC.getOperand(1), Opc1);
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if (Inv0 && !Inv1) {
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std::swap(Tmp1, Tmp2);
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std::swap(Idx0, Idx1);
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Opc = Opc1;
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}
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if (Inv0 && Inv1) Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
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BuildMI(BB, CROpc, 5, Result).addImm(Idx0).addReg(Tmp1).addImm(Idx0)
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.addReg(Tmp2).addImm(Idx1);
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return Result;
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}
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}
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return SelectCCExpr(CC, Opc, Inv, Idx);
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// If this isn't a SetCC, then select the value and compare it against zero,
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// treating it as if it were a boolean.
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Opc = PPC::BNE;
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Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
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Tmp1 = SelectExpr(CC);
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BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
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}
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return Result;
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}
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unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
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unsigned &Idx) {
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bool Inv0, Inv1;
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unsigned Idx0, Idx1, CROpc, Opc1, Tmp1, Tmp2;
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// Allocate a condition register for this expression
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unsigned Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
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// Check for the operations we support:
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switch(N.getOpcode()) {
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default:
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Opc = PPC::BNE;
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Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
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Tmp1 = SelectExpr(N);
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BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
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break;
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case ISD::OR:
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case ISD::AND:
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++MultiBranch;
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Tmp1 = SelectCCExpr(N.getOperand(0), Opc, Inv0, Idx0);
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Tmp2 = SelectCCExpr(N.getOperand(1), Opc1, Inv1, Idx1);
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CROpc = getCROpForSetCC(N.getOpcode(), Inv0, Inv1);
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if (Inv0 && !Inv1) {
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std::swap(Tmp1, Tmp2);
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std::swap(Idx0, Idx1);
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Opc = Opc1;
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}
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if (Inv0 && Inv1) Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
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BuildMI(BB, CROpc, 5, Result).addImm(Idx0).addReg(Tmp1).addImm(Idx0)
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.addReg(Tmp2).addImm(Idx1);
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Inv = false;
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Idx = Idx0;
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break;
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case ISD::SETCC:
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Tmp1 = SelectCC(N, Opc, Inv, Idx);
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Result = Tmp1;
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break;
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}
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return Result;
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}
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/// Check to see if the load is a constant offset from a base register
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bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
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{
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@ -1138,9 +1162,10 @@ void ISel::SelectBranchCC(SDOperand N)
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
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unsigned Opc, CCReg;
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bool Inv;
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unsigned Opc, CCReg, Idx;
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Select(N.getOperand(0)); //chain
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CCReg = SelectCC(N.getOperand(1), Opc);
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CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
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// Iterate to the next basic block, unless we're already at the end of the
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ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
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@ -1258,9 +1283,10 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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return 0;
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}
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bool Inv;
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unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
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unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
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unsigned CCReg = SelectCC(N.getOperand(0), Opc);
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unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
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// Create an iterator with which to insert the MBB for copying the false
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// value and the MBB to hold the PHI instruction for this SetCC.
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@ -1796,6 +1822,15 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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case ISD::AND:
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if (PPCCRopts) {
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if (N.getOperand(0).getOpcode() == ISD::SETCC ||
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N.getOperand(1).getOpcode() == ISD::SETCC) {
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bool Inv;
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Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
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MoveCRtoGPR(Tmp1, Inv, Tmp2, Result);
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return Result;
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}
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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// FIXME: should add check in getImmediateForOpcode to return a value
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// indicating the immediate is a run of set bits so we can emit a bitfield
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@ -1827,6 +1862,15 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::OR:
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if (SelectBitfieldInsert(N, Result))
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return Result;
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if (PPCCRopts) {
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if (N.getOperand(0).getOpcode() == ISD::SETCC ||
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N.getOperand(1).getOpcode() == ISD::SETCC) {
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bool Inv;
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Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
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MoveCRtoGPR(Tmp1, Inv, Tmp2, Result);
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return Result;
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}
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
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default: assert(0 && "unhandled result code");
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@ -2178,30 +2222,19 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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}
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}
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bool Inv = false;
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unsigned CCReg = SelectCC(N, Opc);
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unsigned IntCR = MakeReg(MVT::i32);
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unsigned ShAmt = getCRIdxForBCC(Opc, Inv);
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BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
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BuildMI(BB, PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
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if (Inv) {
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Tmp1 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(ShAmt)
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.addImm(31).addImm(31);
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BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(1);
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} else {
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(IntCR).addImm(ShAmt)
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.addImm(31).addImm(31);
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}
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bool Inv;
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unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
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MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
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return Result;
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}
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assert(0 && "Is this legal?");
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return 0;
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case ISD::SELECT: {
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bool Inv;
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unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
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unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
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unsigned CCReg = SelectCC(N.getOperand(0), Opc);
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unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
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// Create an iterator with which to insert the MBB for copying the false
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// value and the MBB to hold the PHI instruction for this SetCC.
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