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AMDGPU: Update tests for lower i1 change

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I forgot to squash the test updates for b32d3d9e81cdd9275d19cd2a396c461edc9e7189
This commit is contained in:
Matt Arsenault 2021-07-21 16:50:49 -04:00 committed by Matt Arsenault
parent 8979bda8e8
commit 3b4453b968
2 changed files with 9 additions and 13 deletions
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18
test/CodeGen/AMDGPU/loop_break.ll
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@ -115,27 +115,25 @@ define amdgpu_kernel void @undef_phi_cond_break_loop(i32 %arg) #0 {
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: ; implicit-def: $sgpr6_sgpr7 ; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-NEXT: ; implicit-def: $sgpr4 ; GCN-NEXT: ; implicit-def: $sgpr6
; GCN-NEXT: BB1_1: ; %bb1 ; GCN-NEXT: BB1_1: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], s[0:1], exec ; GCN-NEXT: s_cmp_gt_i32 s6, -1
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GCN-NEXT: s_cmp_gt_i32 s4, -1
; GCN-NEXT: s_cbranch_scc1 BB1_3 ; GCN-NEXT: s_cbranch_scc1 BB1_3
; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; %bb.2: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec ; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
; GCN-NEXT: s_and_b64 s[8:9], vcc, exec ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: BB1_3: ; %Flow ; GCN-NEXT: BB1_3: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GCN-NEXT: s_add_i32 s4, s4, 1 ; GCN-NEXT: s_add_i32 s6, s6, 1
; GCN-NEXT: s_and_b64 s[8:9], exec, s[6:7] ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execnz BB1_1 ; GCN-NEXT: s_cbranch_execnz BB1_1

4
test/CodeGen/AMDGPU/sgpr-control-flow.ll
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@ -168,11 +168,9 @@ define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out,
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
; SI-NEXT: s_and_b64 s[8:9], vcc, exec ; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: BB3_2: ; %Flow ; SI-NEXT: BB3_2: ; %Flow
; SI-NEXT: s_or_saveexec_b64 s[2:3], s[2:3] ; SI-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]