From 3b5687a4eb8ac0de99071b7090676f04c3221a39 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Thu, 31 Jan 2019 15:48:46 +0000
Subject: [PATCH] [CGP] add more tests for uaddo; NFC

llvm-svn: 352762
---
 .../CodeGenPrepare/overflow-intrinsics.ll     | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll b/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll
index 46b85347d08..d3d23768980 100644
--- a/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll
+++ b/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -codegenprepare -S < %s | FileCheck %s
 ; RUN: opt -enable-debugify -codegenprepare -S < %s 2>&1 | FileCheck %s -check-prefix=DEBUG
 
@@ -99,6 +100,76 @@ exit:
   ret i64 0
 }
 
+; When adding 1, the general pattern for add-overflow may be different due to icmp canonicalization.
+; PR31754: https://bugs.llvm.org/show_bug.cgi?id=31754
+
+define i1 @uaddo_i64_increment(i64 %x, i64* %p) {
+; CHECK-LABEL: @uaddo_i64_increment(
+; CHECK-NEXT:    [[A:%.*]] = add i64 [[X:%.*]], 1
+; CHECK-NEXT:    [[OV:%.*]] = icmp eq i64 [[A]], 0
+; CHECK-NEXT:    store i64 [[A]], i64* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %a = add i64 %x, 1
+  %ov = icmp eq i64 %a, 0
+  store i64 %a, i64* %p
+  ret i1 %ov
+}
+
+define i1 @uaddo_i8_increment_noncanonical_1(i8 %x, i8* %p) {
+; CHECK-LABEL: @uaddo_i8_increment_noncanonical_1(
+; CHECK-NEXT:    [[A:%.*]] = add i8 1, [[X:%.*]]
+; CHECK-NEXT:    [[OV:%.*]] = icmp eq i8 [[A]], 0
+; CHECK-NEXT:    store i8 [[A]], i8* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %a = add i8 1, %x        ; commute
+  %ov = icmp eq i8 %a, 0
+  store i8 %a, i8* %p
+  ret i1 %ov
+}
+
+define i1 @uaddo_i32_increment_noncanonical_2(i32 %x, i32* %p) {
+; CHECK-LABEL: @uaddo_i32_increment_noncanonical_2(
+; CHECK-NEXT:    [[A:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[OV:%.*]] = icmp eq i32 0, [[A]]
+; CHECK-NEXT:    store i32 [[A]], i32* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %a = add i32 %x, 1
+  %ov = icmp eq i32 0, %a   ; commute
+  store i32 %a, i32* %p
+  ret i1 %ov
+}
+
+define i1 @uaddo_i16_increment_noncanonical_3(i16 %x, i16* %p) {
+; CHECK-LABEL: @uaddo_i16_increment_noncanonical_3(
+; CHECK-NEXT:    [[A:%.*]] = add i16 1, [[X:%.*]]
+; CHECK-NEXT:    [[OV:%.*]] = icmp eq i16 0, [[A]]
+; CHECK-NEXT:    store i16 [[A]], i16* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %a = add i16 1, %x        ; commute
+  %ov = icmp eq i16 0, %a   ; commute
+  store i16 %a, i16* %p
+  ret i1 %ov
+}
+
+; TODO: Did we really intend to match this if it's not supported by the target?
+
+define i1 @uaddo_i42_increment_illegal_type(i42 %x, i42* %p) {
+; CHECK-LABEL: @uaddo_i42_increment_illegal_type(
+; CHECK-NEXT:    [[A:%.*]] = add i42 [[X:%.*]], 1
+; CHECK-NEXT:    [[OV:%.*]] = icmp eq i42 [[A]], 0
+; CHECK-NEXT:    store i42 [[A]], i42* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %a = add i42 %x, 1
+  %ov = icmp eq i42 %a, 0
+  store i42 %a, i42* %p
+  ret i1 %ov
+}
+
 ; Check that every instruction inserted by -codegenprepare has a debug location.
 ; DEBUG: CheckModuleDebugify: PASS