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R600: Expand vector fceil
Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211194
This commit is contained in:
Jan Vesely
parent
e256aa48b9
commit
3b8464bc4e
@ -317,6 +317,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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for (MVT VT : FloatVectorTypes) {
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setOperationAction(ISD::FABS, VT, Expand);
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setOperationAction(ISD::FADD, VT, Expand);
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setOperationAction(ISD::FCEIL, VT, Expand);
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setOperationAction(ISD::FCOS, VT, Expand);
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::FPOW, VT, Expand);
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@ -1,103 +1,131 @@
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; RUN: llc -march=r600 -mcpu=bonaire < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare double @llvm.ceil.f64(double) nounwind readnone
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declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
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declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone
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declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
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declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
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declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
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declare float @llvm.ceil.f32(float) nounwind readnone
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declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone
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declare <3 x float> @llvm.ceil.v3f32(<3 x float>) nounwind readnone
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declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
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declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone
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declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone
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; FUNC-LABEL: @fceil_f64:
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; CI: V_CEIL_F64_e32
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; SI: S_BFE_I32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
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; SI: S_ADD_I32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
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; SI: S_LSHR_B64
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; SI: S_NOT_B64
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; SI: S_AND_B64
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; SI: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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; SI: CMP_LT_I32
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; SI: CNDMASK_B32
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; SI: CNDMASK_B32
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; SI: CMP_GT_I32
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; SI: CNDMASK_B32
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; SI: CNDMASK_B32
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; SI: CMP_GT_F64
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; SI: CNDMASK_B32
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; SI: CMP_NE_I32
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; SI: CNDMASK_B32
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; SI: CNDMASK_B32
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; SI: V_ADD_F64
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define void @fceil_f64(double addrspace(1)* %out, double %x) {
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%y = call double @llvm.ceil.f64(double %x) nounwind readnone
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store double %y, double addrspace(1)* %out
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; FUNC-LABEL: @fceil_f32:
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; SI: V_CEIL_F32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define void @fceil_f32(float addrspace(1)* %out, float %x) {
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%y = call float @llvm.ceil.f32(float %x) nounwind readnone
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store float %y, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fceil_v2f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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define void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
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%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone
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store <2 x double> %y, <2 x double> addrspace(1)* %out
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; FUNC-LABEL: @fceil_v2f32:
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) {
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%y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x) nounwind readnone
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store <2 x float> %y, <2 x float> addrspace(1)* %out
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ret void
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}
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; FIXME-FUNC-LABEL: @fceil_v3f64:
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; FIXME-CI: V_CEIL_F64_e32
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; FIXME-CI: V_CEIL_F64_e32
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; FIXME-CI: V_CEIL_F64_e32
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; define void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
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; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone
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; store <3 x double> %y, <3 x double> addrspace(1)* %out
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; ret void
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; }
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; FUNC-LABEL: @fceil_v4f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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define void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
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%y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
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store <4 x double> %y, <4 x double> addrspace(1)* %out
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; FUNC-LABEL: @fceil_v3f32:
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; FIXME-SI: V_CEIL_F32_e32
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; FIXME-SI: V_CEIL_F32_e32
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; FIXME-SI: V_CEIL_F32_e32
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; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) {
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%y = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) nounwind readnone
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store <3 x float> %y, <3 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fceil_v8f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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define void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
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%y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
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store <8 x double> %y, <8 x double> addrspace(1)* %out
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; FUNC-LABEL: @fceil_v4f32:
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) {
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%y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone
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store <4 x float> %y, <4 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fceil_v16f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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define void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
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%y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone
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store <16 x double> %y, <16 x double> addrspace(1)* %out
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; FUNC-LABEL: @fceil_v8f32:
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) {
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%y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone
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store <8 x float> %y, <8 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fceil_v16f32:
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; SI: V_CEIL_F32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT4:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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define void @fceil_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) {
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%y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone
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store <16 x float> %y, <16 x float> addrspace(1)* %out
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ret void
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}
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103
test/CodeGen/R600/fceil64.ll
Normal file
103
test/CodeGen/R600/fceil64.ll
Normal file
@ -0,0 +1,103 @@
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; RUN: llc -march=r600 -mcpu=bonaire < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare double @llvm.ceil.f64(double) nounwind readnone
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declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
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declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone
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declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
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declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
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declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
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; FUNC-LABEL: @fceil_f64:
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; CI: V_CEIL_F64_e32
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; SI: S_BFE_I32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
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; SI: S_ADD_I32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
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; SI: S_LSHR_B64
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; SI: S_NOT_B64
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; SI: S_AND_B64
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; SI: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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; SI: CMP_LT_I32
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; SI: CNDMASK_B32
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; SI: CNDMASK_B32
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; SI: CMP_GT_I32
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; SI: CNDMASK_B32
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; SI: CNDMASK_B32
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; SI: CMP_GT_F64
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; SI: CNDMASK_B32
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; SI: CMP_NE_I32
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; SI: CNDMASK_B32
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; SI: CNDMASK_B32
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; SI: V_ADD_F64
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define void @fceil_f64(double addrspace(1)* %out, double %x) {
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%y = call double @llvm.ceil.f64(double %x) nounwind readnone
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store double %y, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fceil_v2f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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define void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
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%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone
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store <2 x double> %y, <2 x double> addrspace(1)* %out
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ret void
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}
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; FIXME-FUNC-LABEL: @fceil_v3f64:
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; FIXME-CI: V_CEIL_F64_e32
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; FIXME-CI: V_CEIL_F64_e32
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; FIXME-CI: V_CEIL_F64_e32
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; define void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
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; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone
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; store <3 x double> %y, <3 x double> addrspace(1)* %out
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; ret void
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; }
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; FUNC-LABEL: @fceil_v4f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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define void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
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%y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
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store <4 x double> %y, <4 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fceil_v8f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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define void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
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%y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
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store <8 x double> %y, <8 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fceil_v16f64:
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
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; CI: V_CEIL_F64_e32
|
||||
; CI: V_CEIL_F64_e32
|
||||
; CI: V_CEIL_F64_e32
|
||||
; CI: V_CEIL_F64_e32
|
||||
define void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
|
||||
%y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone
|
||||
store <16 x double> %y, <16 x double> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user