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[InstCombine][AVX2] Add support for simplifying AVX2 per-element shifts to native shifts
Unlike native shifts, the AVX2 per-element shift instructions VPSRAV/VPSRLV/VPSLLV handle out of range shift values (logical shifts set the result to zero, arithmetic shifts splat the sign bit). If the shift amount is constant we can sometimes convert these instructions to native shifts: 1 - if all shift amounts are in range then the conversion is trivial. 2 - out of range arithmetic shifts can be clamped to the (bitwidth - 1) (a legal shift amount) before conversion. 3 - logical shifts just return zero if all elements have out of range shift amounts. In addition, UNDEF shift amounts are handled - either as an UNDEF shift amount in a native shift or as an UNDEF in the logical 'all out of range' zero constant special case for logical shifts. Differential Revision: http://reviews.llvm.org/D19675 llvm-svn: 271996
This commit is contained in:
Simon Pilgrim
parent
6a9d532b78
commit
3b8db9c327
@ -325,6 +325,117 @@ static Value *simplifyX86immShift(const IntrinsicInst &II,
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return Builder.CreateAShr(Vec, ShiftVec);
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}
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// Attempt to simplify AVX2 per-element shift intrinsics to a generic IR shift.
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// Unlike the generic IR shifts, the intrinsics have defined behaviour for out
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// of range shift amounts (logical - set to zero, arithmetic - splat sign bit).
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static Value *simplifyX86varShift(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder) {
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bool LogicalShift = false;
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bool ShiftLeft = false;
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switch (II.getIntrinsicID()) {
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default:
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return nullptr;
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case Intrinsic::x86_avx2_psrav_d:
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case Intrinsic::x86_avx2_psrav_d_256:
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LogicalShift = false;
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ShiftLeft = false;
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break;
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case Intrinsic::x86_avx2_psrlv_d:
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case Intrinsic::x86_avx2_psrlv_d_256:
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case Intrinsic::x86_avx2_psrlv_q:
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case Intrinsic::x86_avx2_psrlv_q_256:
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LogicalShift = true;
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ShiftLeft = false;
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break;
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case Intrinsic::x86_avx2_psllv_d:
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case Intrinsic::x86_avx2_psllv_d_256:
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case Intrinsic::x86_avx2_psllv_q:
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case Intrinsic::x86_avx2_psllv_q_256:
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LogicalShift = true;
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ShiftLeft = true;
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break;
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}
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assert((LogicalShift || !ShiftLeft) && "Only logical shifts can shift left");
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// Simplify if all shift amounts are constant/undef.
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auto *CShift = dyn_cast<Constant>(II.getArgOperand(1));
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if (!CShift)
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return nullptr;
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auto Vec = II.getArgOperand(0);
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auto VT = cast<VectorType>(II.getType());
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auto SVT = VT->getVectorElementType();
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int NumElts = VT->getNumElements();
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int BitWidth = SVT->getIntegerBitWidth();
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// Collect each element's shift amount.
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// We also collect special cases: UNDEF = -1, OUT-OF-RANGE = BitWidth.
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bool AnyOutOfRange = false;
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SmallVector<int, 8> ShiftAmts;
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for (int I = 0; I < NumElts; ++I) {
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auto *CElt = CShift->getAggregateElement(I);
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if (CElt && isa<UndefValue>(CElt)) {
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ShiftAmts.push_back(-1);
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continue;
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}
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auto *COp = dyn_cast_or_null<ConstantInt>(CElt);
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if (!COp)
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return nullptr;
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// Handle out of range shifts.
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// If LogicalShift - set to BitWidth (special case).
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// If ArithmeticShift - set to (BitWidth - 1) (sign splat).
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APInt ShiftVal = COp->getValue();
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if (ShiftVal.uge(BitWidth)) {
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AnyOutOfRange = LogicalShift;
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ShiftAmts.push_back(LogicalShift ? BitWidth : BitWidth - 1);
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continue;
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}
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ShiftAmts.push_back((int)ShiftVal.getZExtValue());
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}
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// If all elements out of range or UNDEF, return vector of zeros/undefs.
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// ArithmeticShift should only hit this if they are all UNDEF.
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auto OutOfRange = [&](int Idx) { return (Idx < 0) || (BitWidth <= Idx); };
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if (llvm::all_of(ShiftAmts, OutOfRange)) {
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SmallVector<Constant *, 8> ConstantVec;
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for (int Idx : ShiftAmts) {
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if (Idx < 0) {
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ConstantVec.push_back(UndefValue::get(SVT));
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} else {
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assert(LogicalShift && "Logical shift expected");
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ConstantVec.push_back(ConstantInt::getNullValue(SVT));
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}
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}
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return ConstantVector::get(ConstantVec);
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}
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// We can't handle only some out of range values with generic logical shifts.
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if (AnyOutOfRange)
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return nullptr;
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// Build the shift amount constant vector.
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SmallVector<Constant *, 8> ShiftVecAmts;
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for (int Idx : ShiftAmts) {
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if (Idx < 0)
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ShiftVecAmts.push_back(UndefValue::get(SVT));
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else
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ShiftVecAmts.push_back(ConstantInt::get(SVT, Idx));
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}
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auto ShiftVec = ConstantVector::get(ShiftVecAmts);
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if (ShiftLeft)
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return Builder.CreateShl(Vec, ShiftVec);
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if (LogicalShift)
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return Builder.CreateLShr(Vec, ShiftVec);
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return Builder.CreateAShr(Vec, ShiftVec);
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}
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static Value *simplifyX86movmsk(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder) {
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Value *Arg = II.getArgOperand(0);
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@ -1656,6 +1767,20 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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break;
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}
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case Intrinsic::x86_avx2_psllv_d:
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case Intrinsic::x86_avx2_psllv_d_256:
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case Intrinsic::x86_avx2_psllv_q:
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case Intrinsic::x86_avx2_psllv_q_256:
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case Intrinsic::x86_avx2_psrav_d:
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case Intrinsic::x86_avx2_psrav_d_256:
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case Intrinsic::x86_avx2_psrlv_d:
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case Intrinsic::x86_avx2_psrlv_d_256:
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case Intrinsic::x86_avx2_psrlv_q:
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case Intrinsic::x86_avx2_psrlv_q_256:
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if (Value *V = simplifyX86varShift(*II, *Builder))
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return replaceInstUsesWith(*II, V);
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break;
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case Intrinsic::x86_sse41_insertps:
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if (Value *V = simplifyX86insertps(*II, *Builder))
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return replaceInstUsesWith(*II, V);
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@ -940,8 +940,7 @@ define <4 x i64> @avx2_psll_q_64(<4 x i64> %v) {
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define <4 x i32> @avx2_psrav_d_128_0(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_128_0(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> zeroinitializer)
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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; CHECK-NEXT: ret <4 x i32> %v
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;
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%1 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> zeroinitializer)
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ret <4 x i32> %1
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@ -949,8 +948,7 @@ define <4 x i32> @avx2_psrav_d_128_0(<4 x i32> %v) {
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define <8 x i32> @avx2_psrav_d_256_0(<8 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_256_0(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
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; CHECK-NEXT: ret <8 x i32> [[TMP1]]
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; CHECK-NEXT: ret <8 x i32> %v
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;
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
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ret <8 x i32> %1
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@ -958,7 +956,7 @@ define <8 x i32> @avx2_psrav_d_256_0(<8 x i32> %v) {
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define <4 x i32> @avx2_psrav_d_128_var(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_128_var(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 64>)
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 0, i32 8, i32 16, i32 31>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 64>)
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@ -967,7 +965,7 @@ define <4 x i32> @avx2_psrav_d_128_var(<4 x i32> %v) {
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define <8 x i32> @avx2_psrav_d_256_var(<8 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_256_var(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>)
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
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; CHECK-NEXT: ret <8 x i32> [[TMP1]]
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;
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>)
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@ -976,7 +974,7 @@ define <8 x i32> @avx2_psrav_d_256_var(<8 x i32> %v) {
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define <4 x i32> @avx2_psrav_d_128_allbig(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_128_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
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@ -985,7 +983,7 @@ define <4 x i32> @avx2_psrav_d_128_allbig(<4 x i32> %v) {
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define <8 x i32> @avx2_psrav_d_256_allbig(<8 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_256_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 undef, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: ret <8 x i32> [[TMP1]]
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;
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
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@ -994,7 +992,7 @@ define <8 x i32> @avx2_psrav_d_256_allbig(<8 x i32> %v) {
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define <4 x i32> @avx2_psrav_d_128_undef(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_128_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> <i32 undef, i32 8, i32 16, i32 64>)
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 undef, i32 8, i32 16, i32 31>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 64>, i32 undef, i32 0
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@ -1004,7 +1002,7 @@ define <4 x i32> @avx2_psrav_d_128_undef(<4 x i32> %v) {
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define <8 x i32> @avx2_psrav_d_256_undef(<8 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_256_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 undef, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>)
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 0, i32 undef, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
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; CHECK-NEXT: ret <8 x i32> [[TMP1]]
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;
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%1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>, i32 undef, i32 1
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@ -1018,8 +1016,7 @@ define <8 x i32> @avx2_psrav_d_256_undef(<8 x i32> %v) {
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define <4 x i32> @avx2_psrlv_d_128_0(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_128_0(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> zeroinitializer)
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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; CHECK-NEXT: ret <4 x i32> %v
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;
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%1 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> zeroinitializer)
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ret <4 x i32> %1
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@ -1027,8 +1024,7 @@ define <4 x i32> @avx2_psrlv_d_128_0(<4 x i32> %v) {
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define <8 x i32> @avx2_psrlv_d_256_0(<8 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_256_0(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
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; CHECK-NEXT: ret <8 x i32> [[TMP1]]
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; CHECK-NEXT: ret <8 x i32> %v
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;
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
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ret <8 x i32> %1
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@ -1036,7 +1032,7 @@ define <8 x i32> @avx2_psrlv_d_256_0(<8 x i32> %v) {
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define <4 x i32> @avx2_psrlv_d_128_var(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_128_var(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 31>)
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> %v, <i32 0, i32 8, i32 16, i32 31>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 31>)
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@ -1045,7 +1041,7 @@ define <4 x i32> @avx2_psrlv_d_128_var(<4 x i32> %v) {
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define <8 x i32> @avx2_psrlv_d_256_var(<8 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_256_var(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
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; CHECK-NEXT: ret <8 x i32> [[TMP1]]
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;
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
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@ -1072,8 +1068,7 @@ define <8 x i32> @avx2_psrlv_d_256_big(<8 x i32> %v) {
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define <4 x i32> @avx2_psrlv_d_128_allbig(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_128_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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; CHECK-NEXT: ret <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
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;
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%1 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
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ret <4 x i32> %1
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@ -1081,8 +1076,7 @@ define <4 x i32> @avx2_psrlv_d_128_allbig(<4 x i32> %v) {
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define <8 x i32> @avx2_psrlv_d_256_allbig(<8 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_256_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
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; CHECK-NEXT: ret <8 x i32> [[TMP1]]
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; CHECK-NEXT: ret <8 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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;
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%1 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
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ret <8 x i32> %1
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@ -1090,7 +1084,7 @@ define <8 x i32> @avx2_psrlv_d_256_allbig(<8 x i32> %v) {
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define <4 x i32> @avx2_psrlv_d_128_undef(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_128_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 undef, i32 8, i32 16, i32 31>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> %v, <i32 undef, i32 8, i32 16, i32 31>
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 undef, i32 0
|
||||
@ -1100,7 +1094,7 @@ define <4 x i32> @avx2_psrlv_d_128_undef(<4 x i32> %v) {
|
||||
|
||||
define <8 x i32> @avx2_psrlv_d_256_undef(<8 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_d_256_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> %v, <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
|
||||
@ -1110,8 +1104,7 @@ define <8 x i32> @avx2_psrlv_d_256_undef(<8 x i32> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psrlv_q_128_0(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_128_0(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> zeroinitializer)
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <2 x i64> %v
|
||||
;
|
||||
%1 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> zeroinitializer)
|
||||
ret <2 x i64> %1
|
||||
@ -1119,8 +1112,7 @@ define <2 x i64> @avx2_psrlv_q_128_0(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psrlv_q_256_0(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_256_0(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <4 x i64> %v
|
||||
;
|
||||
%1 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
|
||||
ret <4 x i64> %1
|
||||
@ -1128,7 +1120,7 @@ define <4 x i64> @avx2_psrlv_q_256_0(<4 x i64> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psrlv_q_128_var(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_128_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> %v, <i64 0, i64 8>
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
|
||||
@ -1137,7 +1129,7 @@ define <2 x i64> @avx2_psrlv_q_128_var(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psrlv_q_256_var(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_256_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> %v, <i64 0, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
|
||||
@ -1164,8 +1156,7 @@ define <4 x i64> @avx2_psrlv_q_256_big(<4 x i64> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psrlv_q_128_allbig(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_128_allbig(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 128, i64 -64>)
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <2 x i64> zeroinitializer
|
||||
;
|
||||
%1 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 128, i64 -64>)
|
||||
ret <2 x i64> %1
|
||||
@ -1173,8 +1164,7 @@ define <2 x i64> @avx2_psrlv_q_128_allbig(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psrlv_q_256_allbig(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_256_allbig(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <4 x i64> <i64 0, i64 undef, i64 0, i64 0>
|
||||
;
|
||||
%1 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
|
||||
ret <4 x i64> %1
|
||||
@ -1182,7 +1172,7 @@ define <4 x i64> @avx2_psrlv_q_256_allbig(<4 x i64> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psrlv_q_128_undef(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_128_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 undef>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> %v, <i64 0, i64 undef>
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <2 x i64> <i64 0, i64 8>, i64 undef, i64 1
|
||||
@ -1192,7 +1182,7 @@ define <2 x i64> @avx2_psrlv_q_128_undef(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psrlv_q_256_undef(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psrlv_q_256_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 undef, i64 8, i64 16, i64 31>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> %v, <i64 undef, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
|
||||
@ -1206,8 +1196,7 @@ define <4 x i64> @avx2_psrlv_q_256_undef(<4 x i64> %v) {
|
||||
|
||||
define <4 x i32> @avx2_psllv_d_128_0(<4 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_128_0(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> zeroinitializer)
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
; CHECK-NEXT: ret <4 x i32> %v
|
||||
;
|
||||
%1 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> zeroinitializer)
|
||||
ret <4 x i32> %1
|
||||
@ -1215,8 +1204,7 @@ define <4 x i32> @avx2_psllv_d_128_0(<4 x i32> %v) {
|
||||
|
||||
define <8 x i32> @avx2_psllv_d_256_0(<8 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_256_0(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
|
||||
; CHECK-NEXT: ret <8 x i32> %v
|
||||
;
|
||||
%1 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
|
||||
ret <8 x i32> %1
|
||||
@ -1224,7 +1212,7 @@ define <8 x i32> @avx2_psllv_d_256_0(<8 x i32> %v) {
|
||||
|
||||
define <4 x i32> @avx2_psllv_d_128_var(<4 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_128_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 31>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> %v, <i32 0, i32 8, i32 16, i32 31>
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 31>)
|
||||
@ -1233,7 +1221,7 @@ define <4 x i32> @avx2_psllv_d_128_var(<4 x i32> %v) {
|
||||
|
||||
define <8 x i32> @avx2_psllv_d_256_var(<8 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_256_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
|
||||
@ -1260,8 +1248,7 @@ define <8 x i32> @avx2_psllv_d_256_big(<8 x i32> %v) {
|
||||
|
||||
define <4 x i32> @avx2_psllv_d_128_allbig(<4 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_128_allbig(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
; CHECK-NEXT: ret <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
|
||||
;
|
||||
%1 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
|
||||
ret <4 x i32> %1
|
||||
@ -1269,8 +1256,7 @@ define <4 x i32> @avx2_psllv_d_128_allbig(<4 x i32> %v) {
|
||||
|
||||
define <8 x i32> @avx2_psllv_d_256_allbig(<8 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_256_allbig(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
|
||||
; CHECK-NEXT: ret <8 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
||||
;
|
||||
%1 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
|
||||
ret <8 x i32> %1
|
||||
@ -1278,7 +1264,7 @@ define <8 x i32> @avx2_psllv_d_256_allbig(<8 x i32> %v) {
|
||||
|
||||
define <4 x i32> @avx2_psllv_d_128_undef(<4 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_128_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 undef, i32 8, i32 16, i32 31>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> %v, <i32 undef, i32 8, i32 16, i32 31>
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 undef, i32 0
|
||||
@ -1288,7 +1274,7 @@ define <4 x i32> @avx2_psllv_d_128_undef(<4 x i32> %v) {
|
||||
|
||||
define <8 x i32> @avx2_psllv_d_256_undef(<8 x i32> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_d_256_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> %v, <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
|
||||
@ -1298,8 +1284,7 @@ define <8 x i32> @avx2_psllv_d_256_undef(<8 x i32> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psllv_q_128_0(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_128_0(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> zeroinitializer)
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <2 x i64> %v
|
||||
;
|
||||
%1 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> zeroinitializer)
|
||||
ret <2 x i64> %1
|
||||
@ -1307,8 +1292,7 @@ define <2 x i64> @avx2_psllv_q_128_0(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psllv_q_256_0(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_256_0(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <4 x i64> %v
|
||||
;
|
||||
%1 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
|
||||
ret <4 x i64> %1
|
||||
@ -1316,7 +1300,7 @@ define <4 x i64> @avx2_psllv_q_256_0(<4 x i64> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psllv_q_128_var(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_128_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i64> %v, <i64 0, i64 8>
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
|
||||
@ -1325,7 +1309,7 @@ define <2 x i64> @avx2_psllv_q_128_var(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psllv_q_256_var(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_256_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> %v, <i64 0, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
|
||||
@ -1352,8 +1336,7 @@ define <4 x i64> @avx2_psllv_q_256_big(<4 x i64> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psllv_q_128_allbig(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_128_allbig(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 128, i64 -64>)
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <2 x i64> zeroinitializer
|
||||
;
|
||||
%1 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 128, i64 -64>)
|
||||
ret <2 x i64> %1
|
||||
@ -1361,8 +1344,7 @@ define <2 x i64> @avx2_psllv_q_128_allbig(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psllv_q_256_allbig(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_256_allbig(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
; CHECK-NEXT: ret <4 x i64> <i64 0, i64 undef, i64 0, i64 0>
|
||||
;
|
||||
%1 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
|
||||
ret <4 x i64> %1
|
||||
@ -1370,7 +1352,7 @@ define <4 x i64> @avx2_psllv_q_256_allbig(<4 x i64> %v) {
|
||||
|
||||
define <2 x i64> @avx2_psllv_q_128_undef(<2 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_128_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 undef>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i64> %v, <i64 0, i64 undef>
|
||||
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <2 x i64> <i64 0, i64 8>, i64 undef, i64 1
|
||||
@ -1380,7 +1362,7 @@ define <2 x i64> @avx2_psllv_q_128_undef(<2 x i64> %v) {
|
||||
|
||||
define <4 x i64> @avx2_psllv_q_256_undef(<4 x i64> %v) {
|
||||
; CHECK-LABEL: @avx2_psllv_q_256_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 undef, i64 8, i64 16, i64 31>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> %v, <i64 undef, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user