From 3baf15621524077ec502c4ed2b502ee9f9113d39 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Mon, 19 Jul 2021 22:52:05 -0700
Subject: [PATCH] [RISCV] Add test cases to show an issue with our fcvt.wu isel
 patterns on RV64.

The pattern we match is (sext_inreg (assertzexti32 (fp_to_uint)), i32). If
the assertzexti32 has an additional user we'll end up emitting
an fcvt.wu and an fcvt.lu.

This can happen if the original fp_to_uint before type legalization
has one user that causes a sext_inreg to be emitted and one that
doesn't.
---
 test/CodeGen/RISCV/double-convert.ll | 168 +++++----
 test/CodeGen/RISCV/float-convert.ll  | 187 +++++-----
 test/CodeGen/RISCV/half-convert.ll   | 489 +++++++++++++++------------
 3 files changed, 480 insertions(+), 364 deletions(-)

diff --git a/test/CodeGen/RISCV/double-convert.ll b/test/CodeGen/RISCV/double-convert.ll
index 29396a58b2c..a30cdaf9157 100644
--- a/test/CodeGen/RISCV/double-convert.ll
+++ b/test/CodeGen/RISCV/double-convert.ll
@@ -139,6 +139,42 @@ define i32 @fcvt_wu_d(double %a) nounwind {
   ret i32 %1
 }
 
+; Test where the fptoui has multiple uses, one of which causes a sext to be
+; inserted on RV64.
+; FIXME: We should not have an fcvt.wu.d and an fcvt.lu.d.
+define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) {
+; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
+; RV32IFD-NEXT:    sw a0, 8(sp)
+; RV32IFD-NEXT:    sw a1, 12(sp)
+; RV32IFD-NEXT:    fld ft0, 8(sp)
+; RV32IFD-NEXT:    fcvt.wu.d a1, ft0, rtz
+; RV32IFD-NEXT:    addi a0, zero, 1
+; RV32IFD-NEXT:    beqz a1, .LBB5_2
+; RV32IFD-NEXT:  # %bb.1:
+; RV32IFD-NEXT:    mv a0, a1
+; RV32IFD-NEXT:  .LBB5_2:
+; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fmv.d.x ft0, a0
+; RV64IFD-NEXT:    fcvt.wu.d a1, ft0, rtz
+; RV64IFD-NEXT:    addi a0, zero, 1
+; RV64IFD-NEXT:    beqz a1, .LBB5_2
+; RV64IFD-NEXT:  # %bb.1:
+; RV64IFD-NEXT:    fcvt.lu.d a0, ft0, rtz
+; RV64IFD-NEXT:  .LBB5_2:
+; RV64IFD-NEXT:    ret
+  %a = fptoui double %x to i32
+  %b = icmp eq i32 %a, 0
+  %c = select i1 %b, i32 1, i32 %a
+  ret i32 %c
+}
+
 define i32 @fcvt_wu_d_sat(double %a) nounwind {
 ; RV32IFD-LABEL: fcvt_wu_d_sat:
 ; RV32IFD:       # %bb.0: # %start
@@ -146,8 +182,8 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV32IFD-NEXT:    fld ft1, %lo(.LCPI5_0)(a0)
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI6_0)
+; RV32IFD-NEXT:    fld ft1, %lo(.LCPI6_0)(a0)
 ; RV32IFD-NEXT:    fcvt.d.w ft2, zero
 ; RV32IFD-NEXT:    fmax.d ft0, ft0, ft2
 ; RV32IFD-NEXT:    fmin.d ft0, ft0, ft1
@@ -157,8 +193,8 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
 ;
 ; RV64IFD-LABEL: fcvt_wu_d_sat:
 ; RV64IFD:       # %bb.0: # %start
-; RV64IFD-NEXT:    lui a1, %hi(.LCPI5_0)
-; RV64IFD-NEXT:    fld ft0, %lo(.LCPI5_0)(a1)
+; RV64IFD-NEXT:    lui a1, %hi(.LCPI6_0)
+; RV64IFD-NEXT:    fld ft0, %lo(.LCPI6_0)(a1)
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, zero
 ; RV64IFD-NEXT:    fmax.d ft1, ft1, ft2
@@ -287,79 +323,79 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
 ; RV32IFD-NEXT:    fsd ft0, 8(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call __fixdfdi@plt
 ; RV32IFD-NEXT:    fld ft1, 8(sp) # 8-byte Folded Reload
-; RV32IFD-NEXT:    lui a2, %hi(.LCPI11_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI11_0)(a2)
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI12_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI12_0)(a2)
 ; RV32IFD-NEXT:    fle.d a3, ft0, ft1
 ; RV32IFD-NEXT:    mv a2, a0
-; RV32IFD-NEXT:    bnez a3, .LBB11_2
+; RV32IFD-NEXT:    bnez a3, .LBB12_2
 ; RV32IFD-NEXT:  # %bb.1: # %start
 ; RV32IFD-NEXT:    mv a2, zero
-; RV32IFD-NEXT:  .LBB11_2: # %start
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI11_1)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI11_1)(a0)
+; RV32IFD-NEXT:  .LBB12_2: # %start
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI12_1)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI12_1)(a0)
 ; RV32IFD-NEXT:    flt.d a4, ft0, ft1
 ; RV32IFD-NEXT:    addi a0, zero, -1
-; RV32IFD-NEXT:    beqz a4, .LBB11_9
+; RV32IFD-NEXT:    beqz a4, .LBB12_9
 ; RV32IFD-NEXT:  # %bb.3: # %start
 ; RV32IFD-NEXT:    feq.d a2, ft1, ft1
-; RV32IFD-NEXT:    beqz a2, .LBB11_10
-; RV32IFD-NEXT:  .LBB11_4: # %start
+; RV32IFD-NEXT:    beqz a2, .LBB12_10
+; RV32IFD-NEXT:  .LBB12_4: # %start
 ; RV32IFD-NEXT:    lui a5, 524288
-; RV32IFD-NEXT:    beqz a3, .LBB11_11
-; RV32IFD-NEXT:  .LBB11_5: # %start
-; RV32IFD-NEXT:    bnez a4, .LBB11_12
-; RV32IFD-NEXT:  .LBB11_6: # %start
-; RV32IFD-NEXT:    bnez a2, .LBB11_8
-; RV32IFD-NEXT:  .LBB11_7: # %start
+; RV32IFD-NEXT:    beqz a3, .LBB12_11
+; RV32IFD-NEXT:  .LBB12_5: # %start
+; RV32IFD-NEXT:    bnez a4, .LBB12_12
+; RV32IFD-NEXT:  .LBB12_6: # %start
+; RV32IFD-NEXT:    bnez a2, .LBB12_8
+; RV32IFD-NEXT:  .LBB12_7: # %start
 ; RV32IFD-NEXT:    mv a1, zero
-; RV32IFD-NEXT:  .LBB11_8: # %start
+; RV32IFD-NEXT:  .LBB12_8: # %start
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB11_9: # %start
+; RV32IFD-NEXT:  .LBB12_9: # %start
 ; RV32IFD-NEXT:    mv a0, a2
 ; RV32IFD-NEXT:    feq.d a2, ft1, ft1
-; RV32IFD-NEXT:    bnez a2, .LBB11_4
-; RV32IFD-NEXT:  .LBB11_10: # %start
+; RV32IFD-NEXT:    bnez a2, .LBB12_4
+; RV32IFD-NEXT:  .LBB12_10: # %start
 ; RV32IFD-NEXT:    mv a0, zero
 ; RV32IFD-NEXT:    lui a5, 524288
-; RV32IFD-NEXT:    bnez a3, .LBB11_5
-; RV32IFD-NEXT:  .LBB11_11: # %start
+; RV32IFD-NEXT:    bnez a3, .LBB12_5
+; RV32IFD-NEXT:  .LBB12_11: # %start
 ; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    beqz a4, .LBB11_6
-; RV32IFD-NEXT:  .LBB11_12:
+; RV32IFD-NEXT:    beqz a4, .LBB12_6
+; RV32IFD-NEXT:  .LBB12_12:
 ; RV32IFD-NEXT:    addi a1, a5, -1
-; RV32IFD-NEXT:    beqz a2, .LBB11_7
-; RV32IFD-NEXT:    j .LBB11_8
+; RV32IFD-NEXT:    beqz a2, .LBB12_7
+; RV32IFD-NEXT:    j .LBB12_8
 ;
 ; RV64IFD-LABEL: fcvt_l_d_sat:
 ; RV64IFD:       # %bb.0: # %start
-; RV64IFD-NEXT:    lui a1, %hi(.LCPI11_0)
-; RV64IFD-NEXT:    fld ft1, %lo(.LCPI11_0)(a1)
+; RV64IFD-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV64IFD-NEXT:    fld ft1, %lo(.LCPI12_0)(a1)
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fle.d a0, ft1, ft0
 ; RV64IFD-NEXT:    addi a1, zero, -1
-; RV64IFD-NEXT:    bnez a0, .LBB11_2
+; RV64IFD-NEXT:    bnez a0, .LBB12_2
 ; RV64IFD-NEXT:  # %bb.1: # %start
 ; RV64IFD-NEXT:    slli a0, a1, 63
-; RV64IFD-NEXT:    j .LBB11_3
-; RV64IFD-NEXT:  .LBB11_2:
+; RV64IFD-NEXT:    j .LBB12_3
+; RV64IFD-NEXT:  .LBB12_2:
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64IFD-NEXT:  .LBB11_3: # %start
-; RV64IFD-NEXT:    lui a2, %hi(.LCPI11_1)
-; RV64IFD-NEXT:    fld ft1, %lo(.LCPI11_1)(a2)
+; RV64IFD-NEXT:  .LBB12_3: # %start
+; RV64IFD-NEXT:    lui a2, %hi(.LCPI12_1)
+; RV64IFD-NEXT:    fld ft1, %lo(.LCPI12_1)(a2)
 ; RV64IFD-NEXT:    flt.d a2, ft1, ft0
-; RV64IFD-NEXT:    bnez a2, .LBB11_6
+; RV64IFD-NEXT:    bnez a2, .LBB12_6
 ; RV64IFD-NEXT:  # %bb.4: # %start
 ; RV64IFD-NEXT:    feq.d a1, ft0, ft0
-; RV64IFD-NEXT:    beqz a1, .LBB11_7
-; RV64IFD-NEXT:  .LBB11_5: # %start
+; RV64IFD-NEXT:    beqz a1, .LBB12_7
+; RV64IFD-NEXT:  .LBB12_5: # %start
 ; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB11_6:
+; RV64IFD-NEXT:  .LBB12_6:
 ; RV64IFD-NEXT:    srli a0, a1, 1
 ; RV64IFD-NEXT:    feq.d a1, ft0, ft0
-; RV64IFD-NEXT:    bnez a1, .LBB11_5
-; RV64IFD-NEXT:  .LBB11_7: # %start
+; RV64IFD-NEXT:    bnez a1, .LBB12_5
+; RV64IFD-NEXT:  .LBB12_7: # %start
 ; RV64IFD-NEXT:    mv a0, zero
 ; RV64IFD-NEXT:    ret
 start:
@@ -401,55 +437,55 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
 ; RV32IFD-NEXT:    fle.d a4, ft0, ft1
 ; RV32IFD-NEXT:    mv a3, a0
-; RV32IFD-NEXT:    bnez a4, .LBB13_2
+; RV32IFD-NEXT:    bnez a4, .LBB14_2
 ; RV32IFD-NEXT:  # %bb.1: # %start
 ; RV32IFD-NEXT:    mv a3, zero
-; RV32IFD-NEXT:  .LBB13_2: # %start
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI13_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI13_0)(a0)
+; RV32IFD-NEXT:  .LBB14_2: # %start
+; RV32IFD-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI14_0)(a0)
 ; RV32IFD-NEXT:    flt.d a5, ft0, ft1
 ; RV32IFD-NEXT:    addi a2, zero, -1
 ; RV32IFD-NEXT:    addi a0, zero, -1
-; RV32IFD-NEXT:    beqz a5, .LBB13_7
+; RV32IFD-NEXT:    beqz a5, .LBB14_7
 ; RV32IFD-NEXT:  # %bb.3: # %start
-; RV32IFD-NEXT:    beqz a4, .LBB13_8
-; RV32IFD-NEXT:  .LBB13_4: # %start
-; RV32IFD-NEXT:    bnez a5, .LBB13_6
-; RV32IFD-NEXT:  .LBB13_5: # %start
+; RV32IFD-NEXT:    beqz a4, .LBB14_8
+; RV32IFD-NEXT:  .LBB14_4: # %start
+; RV32IFD-NEXT:    bnez a5, .LBB14_6
+; RV32IFD-NEXT:  .LBB14_5: # %start
 ; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:  .LBB13_6: # %start
+; RV32IFD-NEXT:  .LBB14_6: # %start
 ; RV32IFD-NEXT:    mv a1, a2
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB13_7: # %start
+; RV32IFD-NEXT:  .LBB14_7: # %start
 ; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bnez a4, .LBB13_4
-; RV32IFD-NEXT:  .LBB13_8: # %start
+; RV32IFD-NEXT:    bnez a4, .LBB14_4
+; RV32IFD-NEXT:  .LBB14_8: # %start
 ; RV32IFD-NEXT:    mv a1, zero
-; RV32IFD-NEXT:    beqz a5, .LBB13_5
-; RV32IFD-NEXT:    j .LBB13_6
+; RV32IFD-NEXT:    beqz a5, .LBB14_5
+; RV32IFD-NEXT:    j .LBB14_6
 ;
 ; RV64IFD-LABEL: fcvt_lu_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fmv.d.x ft1, zero
 ; RV64IFD-NEXT:    fle.d a0, ft1, ft0
-; RV64IFD-NEXT:    bnez a0, .LBB13_2
+; RV64IFD-NEXT:    bnez a0, .LBB14_2
 ; RV64IFD-NEXT:  # %bb.1: # %start
 ; RV64IFD-NEXT:    mv a1, zero
-; RV64IFD-NEXT:    j .LBB13_3
-; RV64IFD-NEXT:  .LBB13_2:
+; RV64IFD-NEXT:    j .LBB14_3
+; RV64IFD-NEXT:  .LBB14_2:
 ; RV64IFD-NEXT:    fcvt.lu.d a1, ft0, rtz
-; RV64IFD-NEXT:  .LBB13_3: # %start
-; RV64IFD-NEXT:    lui a0, %hi(.LCPI13_0)
-; RV64IFD-NEXT:    fld ft1, %lo(.LCPI13_0)(a0)
+; RV64IFD-NEXT:  .LBB14_3: # %start
+; RV64IFD-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV64IFD-NEXT:    fld ft1, %lo(.LCPI14_0)(a0)
 ; RV64IFD-NEXT:    flt.d a2, ft1, ft0
 ; RV64IFD-NEXT:    addi a0, zero, -1
-; RV64IFD-NEXT:    bnez a2, .LBB13_5
+; RV64IFD-NEXT:    bnez a2, .LBB14_5
 ; RV64IFD-NEXT:  # %bb.4: # %start
 ; RV64IFD-NEXT:    mv a0, a1
-; RV64IFD-NEXT:  .LBB13_5: # %start
+; RV64IFD-NEXT:  .LBB14_5: # %start
 ; RV64IFD-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
diff --git a/test/CodeGen/RISCV/float-convert.ll b/test/CodeGen/RISCV/float-convert.ll
index 97a97f8ef4b..699c7604221 100644
--- a/test/CodeGen/RISCV/float-convert.ll
+++ b/test/CodeGen/RISCV/float-convert.ll
@@ -108,27 +108,58 @@ define i32 @fcvt_wu_s(float %a) nounwind {
   ret i32 %1
 }
 
+; Test where the fptoui has multiple uses, one of which causes a sext to be
+; inserted on RV64.
+; FIXME: We should not have an fcvt.wu.s and an fcvt.lu.s.
+define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
+; RV32IF-LABEL: fcvt_wu_s_multiple_use:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fcvt.wu.s a1, ft0, rtz
+; RV32IF-NEXT:    addi a0, zero, 1
+; RV32IF-NEXT:    beqz a1, .LBB3_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    mv a0, a1
+; RV32IF-NEXT:  .LBB3_2:
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcvt_wu_s_multiple_use:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    fcvt.wu.s a1, ft0, rtz
+; RV64IF-NEXT:    addi a0, zero, 1
+; RV64IF-NEXT:    beqz a1, .LBB3_2
+; RV64IF-NEXT:  # %bb.1:
+; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT:  .LBB3_2:
+; RV64IF-NEXT:    ret
+  %a = fptoui float %x to i32
+  %b = icmp eq i32 %a, 0
+  %c = select i1 %b, i32 1, i32 %a
+  ret i32 %c
+}
+
 define i32 @fcvt_wu_s_sat(float %a) nounwind {
 ; RV32IF-LABEL: fcvt_wu_s_sat:
 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fmv.w.x ft1, zero
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
-; RV32IF-NEXT:    bnez a0, .LBB3_2
+; RV32IF-NEXT:    bnez a0, .LBB4_2
 ; RV32IF-NEXT:  # %bb.1: # %start
 ; RV32IF-NEXT:    mv a1, zero
-; RV32IF-NEXT:    j .LBB3_3
-; RV32IF-NEXT:  .LBB3_2:
+; RV32IF-NEXT:    j .LBB4_3
+; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    fcvt.wu.s a1, ft0, rtz
-; RV32IF-NEXT:  .LBB3_3: # %start
-; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32IF-NEXT:    flw ft1, %lo(.LCPI3_0)(a0)
+; RV32IF-NEXT:  .LBB4_3: # %start
+; RV32IF-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV32IF-NEXT:    flw ft1, %lo(.LCPI4_0)(a0)
 ; RV32IF-NEXT:    flt.s a2, ft1, ft0
 ; RV32IF-NEXT:    addi a0, zero, -1
-; RV32IF-NEXT:    bnez a2, .LBB3_5
+; RV32IF-NEXT:    bnez a2, .LBB4_5
 ; RV32IF-NEXT:  # %bb.4: # %start
 ; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB3_5: # %start
+; RV32IF-NEXT:  .LBB4_5: # %start
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_wu_s_sat:
@@ -136,21 +167,21 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fmv.w.x ft1, zero
 ; RV64IF-NEXT:    fle.s a0, ft1, ft0
-; RV64IF-NEXT:    bnez a0, .LBB3_2
+; RV64IF-NEXT:    bnez a0, .LBB4_2
 ; RV64IF-NEXT:  # %bb.1: # %start
 ; RV64IF-NEXT:    mv a0, zero
-; RV64IF-NEXT:    j .LBB3_3
-; RV64IF-NEXT:  .LBB3_2:
+; RV64IF-NEXT:    j .LBB4_3
+; RV64IF-NEXT:  .LBB4_2:
 ; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64IF-NEXT:  .LBB3_3: # %start
-; RV64IF-NEXT:    lui a1, %hi(.LCPI3_0)
-; RV64IF-NEXT:    flw ft1, %lo(.LCPI3_0)(a1)
+; RV64IF-NEXT:  .LBB4_3: # %start
+; RV64IF-NEXT:    lui a1, %hi(.LCPI4_0)
+; RV64IF-NEXT:    flw ft1, %lo(.LCPI4_0)(a1)
 ; RV64IF-NEXT:    flt.s a1, ft1, ft0
-; RV64IF-NEXT:    beqz a1, .LBB3_5
+; RV64IF-NEXT:    beqz a1, .LBB4_5
 ; RV64IF-NEXT:  # %bb.4:
 ; RV64IF-NEXT:    addi a0, zero, -1
 ; RV64IF-NEXT:    srli a0, a0, 32
-; RV64IF-NEXT:  .LBB3_5: # %start
+; RV64IF-NEXT:  .LBB4_5: # %start
 ; RV64IF-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
@@ -298,85 +329,85 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    lui a1, %hi(.LCPI11_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a1)
+; RV32IF-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_0)(a1)
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fsw ft1, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fle.s s0, ft0, ft1
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    mv a2, a0
-; RV32IF-NEXT:    bnez s0, .LBB11_2
+; RV32IF-NEXT:    bnez s0, .LBB12_2
 ; RV32IF-NEXT:  # %bb.1: # %start
 ; RV32IF-NEXT:    mv a2, zero
-; RV32IF-NEXT:  .LBB11_2: # %start
-; RV32IF-NEXT:    lui a0, %hi(.LCPI11_1)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_1)(a0)
+; RV32IF-NEXT:  .LBB12_2: # %start
+; RV32IF-NEXT:    lui a0, %hi(.LCPI12_1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_1)(a0)
 ; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flt.s a3, ft0, ft1
 ; RV32IF-NEXT:    fmv.s ft0, ft1
 ; RV32IF-NEXT:    addi a0, zero, -1
-; RV32IF-NEXT:    beqz a3, .LBB11_9
+; RV32IF-NEXT:    beqz a3, .LBB12_9
 ; RV32IF-NEXT:  # %bb.3: # %start
 ; RV32IF-NEXT:    feq.s a2, ft0, ft0
-; RV32IF-NEXT:    beqz a2, .LBB11_10
-; RV32IF-NEXT:  .LBB11_4: # %start
+; RV32IF-NEXT:    beqz a2, .LBB12_10
+; RV32IF-NEXT:  .LBB12_4: # %start
 ; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    beqz s0, .LBB11_11
-; RV32IF-NEXT:  .LBB11_5: # %start
-; RV32IF-NEXT:    bnez a3, .LBB11_12
-; RV32IF-NEXT:  .LBB11_6: # %start
-; RV32IF-NEXT:    bnez a2, .LBB11_8
-; RV32IF-NEXT:  .LBB11_7: # %start
+; RV32IF-NEXT:    beqz s0, .LBB12_11
+; RV32IF-NEXT:  .LBB12_5: # %start
+; RV32IF-NEXT:    bnez a3, .LBB12_12
+; RV32IF-NEXT:  .LBB12_6: # %start
+; RV32IF-NEXT:    bnez a2, .LBB12_8
+; RV32IF-NEXT:  .LBB12_7: # %start
 ; RV32IF-NEXT:    mv a1, zero
-; RV32IF-NEXT:  .LBB11_8: # %start
+; RV32IF-NEXT:  .LBB12_8: # %start
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB11_9: # %start
+; RV32IF-NEXT:  .LBB12_9: # %start
 ; RV32IF-NEXT:    mv a0, a2
 ; RV32IF-NEXT:    feq.s a2, ft0, ft0
-; RV32IF-NEXT:    bnez a2, .LBB11_4
-; RV32IF-NEXT:  .LBB11_10: # %start
+; RV32IF-NEXT:    bnez a2, .LBB12_4
+; RV32IF-NEXT:  .LBB12_10: # %start
 ; RV32IF-NEXT:    mv a0, zero
 ; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    bnez s0, .LBB11_5
-; RV32IF-NEXT:  .LBB11_11: # %start
+; RV32IF-NEXT:    bnez s0, .LBB12_5
+; RV32IF-NEXT:  .LBB12_11: # %start
 ; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    beqz a3, .LBB11_6
-; RV32IF-NEXT:  .LBB11_12:
+; RV32IF-NEXT:    beqz a3, .LBB12_6
+; RV32IF-NEXT:  .LBB12_12:
 ; RV32IF-NEXT:    addi a1, a4, -1
-; RV32IF-NEXT:    beqz a2, .LBB11_7
-; RV32IF-NEXT:    j .LBB11_8
+; RV32IF-NEXT:    beqz a2, .LBB12_7
+; RV32IF-NEXT:    j .LBB12_8
 ;
 ; RV64IF-LABEL: fcvt_l_s_sat:
 ; RV64IF:       # %bb.0: # %start
-; RV64IF-NEXT:    lui a1, %hi(.LCPI11_0)
-; RV64IF-NEXT:    flw ft1, %lo(.LCPI11_0)(a1)
+; RV64IF-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV64IF-NEXT:    flw ft1, %lo(.LCPI12_0)(a1)
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fle.s a0, ft1, ft0
 ; RV64IF-NEXT:    addi a1, zero, -1
-; RV64IF-NEXT:    bnez a0, .LBB11_2
+; RV64IF-NEXT:    bnez a0, .LBB12_2
 ; RV64IF-NEXT:  # %bb.1: # %start
 ; RV64IF-NEXT:    slli a0, a1, 63
-; RV64IF-NEXT:    j .LBB11_3
-; RV64IF-NEXT:  .LBB11_2:
+; RV64IF-NEXT:    j .LBB12_3
+; RV64IF-NEXT:  .LBB12_2:
 ; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64IF-NEXT:  .LBB11_3: # %start
-; RV64IF-NEXT:    lui a2, %hi(.LCPI11_1)
-; RV64IF-NEXT:    flw ft1, %lo(.LCPI11_1)(a2)
+; RV64IF-NEXT:  .LBB12_3: # %start
+; RV64IF-NEXT:    lui a2, %hi(.LCPI12_1)
+; RV64IF-NEXT:    flw ft1, %lo(.LCPI12_1)(a2)
 ; RV64IF-NEXT:    flt.s a2, ft1, ft0
-; RV64IF-NEXT:    bnez a2, .LBB11_6
+; RV64IF-NEXT:    bnez a2, .LBB12_6
 ; RV64IF-NEXT:  # %bb.4: # %start
 ; RV64IF-NEXT:    feq.s a1, ft0, ft0
-; RV64IF-NEXT:    beqz a1, .LBB11_7
-; RV64IF-NEXT:  .LBB11_5: # %start
+; RV64IF-NEXT:    beqz a1, .LBB12_7
+; RV64IF-NEXT:  .LBB12_5: # %start
 ; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB11_6:
+; RV64IF-NEXT:  .LBB12_6:
 ; RV64IF-NEXT:    srli a0, a1, 1
 ; RV64IF-NEXT:    feq.s a1, ft0, ft0
-; RV64IF-NEXT:    bnez a1, .LBB11_5
-; RV64IF-NEXT:  .LBB11_7: # %start
+; RV64IF-NEXT:    bnez a1, .LBB12_5
+; RV64IF-NEXT:  .LBB12_7: # %start
 ; RV64IF-NEXT:    mv a0, zero
 ; RV64IF-NEXT:    ret
 start:
@@ -416,57 +447,57 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
 ; RV32IF-NEXT:    fle.s s0, ft0, ft1
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    mv a3, a0
-; RV32IF-NEXT:    bnez s0, .LBB13_2
+; RV32IF-NEXT:    bnez s0, .LBB14_2
 ; RV32IF-NEXT:  # %bb.1: # %start
 ; RV32IF-NEXT:    mv a3, zero
-; RV32IF-NEXT:  .LBB13_2: # %start
-; RV32IF-NEXT:    lui a0, %hi(.LCPI13_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_0)(a0)
+; RV32IF-NEXT:  .LBB14_2: # %start
+; RV32IF-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI14_0)(a0)
 ; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flt.s a4, ft0, ft1
 ; RV32IF-NEXT:    addi a2, zero, -1
 ; RV32IF-NEXT:    addi a0, zero, -1
-; RV32IF-NEXT:    beqz a4, .LBB13_7
+; RV32IF-NEXT:    beqz a4, .LBB14_7
 ; RV32IF-NEXT:  # %bb.3: # %start
-; RV32IF-NEXT:    beqz s0, .LBB13_8
-; RV32IF-NEXT:  .LBB13_4: # %start
-; RV32IF-NEXT:    bnez a4, .LBB13_6
-; RV32IF-NEXT:  .LBB13_5: # %start
+; RV32IF-NEXT:    beqz s0, .LBB14_8
+; RV32IF-NEXT:  .LBB14_4: # %start
+; RV32IF-NEXT:    bnez a4, .LBB14_6
+; RV32IF-NEXT:  .LBB14_5: # %start
 ; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:  .LBB13_6: # %start
+; RV32IF-NEXT:  .LBB14_6: # %start
 ; RV32IF-NEXT:    mv a1, a2
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB13_7: # %start
+; RV32IF-NEXT:  .LBB14_7: # %start
 ; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bnez s0, .LBB13_4
-; RV32IF-NEXT:  .LBB13_8: # %start
+; RV32IF-NEXT:    bnez s0, .LBB14_4
+; RV32IF-NEXT:  .LBB14_8: # %start
 ; RV32IF-NEXT:    mv a1, zero
-; RV32IF-NEXT:    beqz a4, .LBB13_5
-; RV32IF-NEXT:    j .LBB13_6
+; RV32IF-NEXT:    beqz a4, .LBB14_5
+; RV32IF-NEXT:    j .LBB14_6
 ;
 ; RV64IF-LABEL: fcvt_lu_s_sat:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fmv.w.x ft1, zero
 ; RV64IF-NEXT:    fle.s a0, ft1, ft0
-; RV64IF-NEXT:    bnez a0, .LBB13_2
+; RV64IF-NEXT:    bnez a0, .LBB14_2
 ; RV64IF-NEXT:  # %bb.1: # %start
 ; RV64IF-NEXT:    mv a1, zero
-; RV64IF-NEXT:    j .LBB13_3
-; RV64IF-NEXT:  .LBB13_2:
+; RV64IF-NEXT:    j .LBB14_3
+; RV64IF-NEXT:  .LBB14_2:
 ; RV64IF-NEXT:    fcvt.lu.s a1, ft0, rtz
-; RV64IF-NEXT:  .LBB13_3: # %start
-; RV64IF-NEXT:    lui a0, %hi(.LCPI13_0)
-; RV64IF-NEXT:    flw ft1, %lo(.LCPI13_0)(a0)
+; RV64IF-NEXT:  .LBB14_3: # %start
+; RV64IF-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV64IF-NEXT:    flw ft1, %lo(.LCPI14_0)(a0)
 ; RV64IF-NEXT:    flt.s a2, ft1, ft0
 ; RV64IF-NEXT:    addi a0, zero, -1
-; RV64IF-NEXT:    bnez a2, .LBB13_5
+; RV64IF-NEXT:    bnez a2, .LBB14_5
 ; RV64IF-NEXT:  # %bb.4: # %start
 ; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB13_5: # %start
+; RV64IF-NEXT:  .LBB14_5: # %start
 ; RV64IF-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
diff --git a/test/CodeGen/RISCV/half-convert.ll b/test/CodeGen/RISCV/half-convert.ll
index 4895f75e411..6630c9b9212 100644
--- a/test/CodeGen/RISCV/half-convert.ll
+++ b/test/CodeGen/RISCV/half-convert.ll
@@ -134,11 +134,60 @@ define i16 @fcvt_ui_h(half %a) nounwind {
   ret i16 %1
 }
 
+; Test where the fptoui has multiple uses, one of which causes a sext to be
+; inserted on RV64.
+; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
+define i32 @fcvt_ui_h_multiple_use(half %x, i32* %y) {
+; RV32IZFH-LABEL: fcvt_ui_h_multiple_use:
+; RV32IZFH:       # %bb.0:
+; RV32IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
+; RV32IZFH-NEXT:    addi a0, zero, 1
+; RV32IZFH-NEXT:    beqz a1, .LBB3_2
+; RV32IZFH-NEXT:  # %bb.1:
+; RV32IZFH-NEXT:    mv a0, a1
+; RV32IZFH-NEXT:  .LBB3_2:
+; RV32IZFH-NEXT:    ret
+;
+; RV32IDZFH-LABEL: fcvt_ui_h_multiple_use:
+; RV32IDZFH:       # %bb.0:
+; RV32IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
+; RV32IDZFH-NEXT:    addi a0, zero, 1
+; RV32IDZFH-NEXT:    beqz a1, .LBB3_2
+; RV32IDZFH-NEXT:  # %bb.1:
+; RV32IDZFH-NEXT:    mv a0, a1
+; RV32IDZFH-NEXT:  .LBB3_2:
+; RV32IDZFH-NEXT:    ret
+;
+; RV64IZFH-LABEL: fcvt_ui_h_multiple_use:
+; RV64IZFH:       # %bb.0:
+; RV64IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
+; RV64IZFH-NEXT:    addi a0, zero, 1
+; RV64IZFH-NEXT:    beqz a1, .LBB3_2
+; RV64IZFH-NEXT:  # %bb.1:
+; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB3_2:
+; RV64IZFH-NEXT:    ret
+;
+; RV64IDZFH-LABEL: fcvt_ui_h_multiple_use:
+; RV64IDZFH:       # %bb.0:
+; RV64IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
+; RV64IDZFH-NEXT:    addi a0, zero, 1
+; RV64IDZFH-NEXT:    beqz a1, .LBB3_2
+; RV64IDZFH-NEXT:  # %bb.1:
+; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
+; RV64IDZFH-NEXT:  .LBB3_2:
+; RV64IDZFH-NEXT:    ret
+  %a = fptoui half %x to i32
+  %b = icmp eq i32 %a, 0
+  %c = select i1 %b, i32 1, i32 %a
+  ret i32 %c
+}
+
 define i16 @fcvt_ui_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_ui_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.s.h ft1, fa0
 ; RV32IZFH-NEXT:    fmv.w.x ft2, zero
 ; RV32IZFH-NEXT:    fmax.s ft1, ft1, ft2
@@ -148,8 +197,8 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
 ;
 ; RV32IDZFH-LABEL: fcvt_ui_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
 ; RV32IDZFH-NEXT:    fcvt.s.h ft1, fa0
 ; RV32IDZFH-NEXT:    fmv.w.x ft2, zero
 ; RV32IDZFH-NEXT:    fmax.s ft1, ft1, ft2
@@ -159,8 +208,8 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
 ;
 ; RV64IZFH-LABEL: fcvt_ui_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
-; RV64IZFH-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV64IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; RV64IZFH-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV64IZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
 ; RV64IZFH-NEXT:    fcvt.s.h ft1, fa0
 ; RV64IZFH-NEXT:    fmv.w.x ft2, zero
 ; RV64IZFH-NEXT:    fmax.s ft1, ft1, ft2
@@ -170,8 +219,8 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
 ;
 ; RV64IDZFH-LABEL: fcvt_ui_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
-; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV64IDZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
+; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI4_0)
+; RV64IDZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
 ; RV64IDZFH-NEXT:    fcvt.s.h ft1, fa0
 ; RV64IDZFH-NEXT:    fmv.w.x ft2, zero
 ; RV64IDZFH-NEXT:    fmax.s ft1, ft1, ft2
@@ -211,125 +260,125 @@ define i32 @fcvt_w_h(half %a) nounwind {
 define i32 @fcvt_w_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI6_0)
+; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IZFH-NEXT:    fle.s a0, ft1, ft0
 ; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    bnez a0, .LBB5_2
+; RV32IZFH-NEXT:    bnez a0, .LBB6_2
 ; RV32IZFH-NEXT:  # %bb.1: # %start
 ; RV32IZFH-NEXT:    lui a0, 524288
-; RV32IZFH-NEXT:    j .LBB5_3
-; RV32IZFH-NEXT:  .LBB5_2:
+; RV32IZFH-NEXT:    j .LBB6_3
+; RV32IZFH-NEXT:  .LBB6_2:
 ; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32IZFH-NEXT:  .LBB5_3: # %start
-; RV32IZFH-NEXT:    lui a2, %hi(.LCPI5_1)
-; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
+; RV32IZFH-NEXT:  .LBB6_3: # %start
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI6_1)
+; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
 ; RV32IZFH-NEXT:    flt.s a2, ft1, ft0
-; RV32IZFH-NEXT:    bnez a2, .LBB5_6
+; RV32IZFH-NEXT:    bnez a2, .LBB6_6
 ; RV32IZFH-NEXT:  # %bb.4: # %start
 ; RV32IZFH-NEXT:    feq.s a1, ft0, ft0
-; RV32IZFH-NEXT:    beqz a1, .LBB5_7
-; RV32IZFH-NEXT:  .LBB5_5: # %start
+; RV32IZFH-NEXT:    beqz a1, .LBB6_7
+; RV32IZFH-NEXT:  .LBB6_5: # %start
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB5_6:
+; RV32IZFH-NEXT:  .LBB6_6:
 ; RV32IZFH-NEXT:    addi a0, a1, -1
 ; RV32IZFH-NEXT:    feq.s a1, ft0, ft0
-; RV32IZFH-NEXT:    bnez a1, .LBB5_5
-; RV32IZFH-NEXT:  .LBB5_7: # %start
+; RV32IZFH-NEXT:    bnez a1, .LBB6_5
+; RV32IZFH-NEXT:  .LBB6_7: # %start
 ; RV32IZFH-NEXT:    mv a0, zero
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI6_0)
+; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
 ; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IDZFH-NEXT:    fle.s a0, ft1, ft0
 ; RV32IDZFH-NEXT:    lui a1, 524288
-; RV32IDZFH-NEXT:    bnez a0, .LBB5_2
+; RV32IDZFH-NEXT:    bnez a0, .LBB6_2
 ; RV32IDZFH-NEXT:  # %bb.1: # %start
 ; RV32IDZFH-NEXT:    lui a0, 524288
-; RV32IDZFH-NEXT:    j .LBB5_3
-; RV32IDZFH-NEXT:  .LBB5_2:
+; RV32IDZFH-NEXT:    j .LBB6_3
+; RV32IDZFH-NEXT:  .LBB6_2:
 ; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32IDZFH-NEXT:  .LBB5_3: # %start
-; RV32IDZFH-NEXT:    lui a2, %hi(.LCPI5_1)
-; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
+; RV32IDZFH-NEXT:  .LBB6_3: # %start
+; RV32IDZFH-NEXT:    lui a2, %hi(.LCPI6_1)
+; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
 ; RV32IDZFH-NEXT:    flt.s a2, ft1, ft0
-; RV32IDZFH-NEXT:    bnez a2, .LBB5_6
+; RV32IDZFH-NEXT:    bnez a2, .LBB6_6
 ; RV32IDZFH-NEXT:  # %bb.4: # %start
 ; RV32IDZFH-NEXT:    feq.s a1, ft0, ft0
-; RV32IDZFH-NEXT:    beqz a1, .LBB5_7
-; RV32IDZFH-NEXT:  .LBB5_5: # %start
+; RV32IDZFH-NEXT:    beqz a1, .LBB6_7
+; RV32IDZFH-NEXT:  .LBB6_5: # %start
 ; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB5_6:
+; RV32IDZFH-NEXT:  .LBB6_6:
 ; RV32IDZFH-NEXT:    addi a0, a1, -1
 ; RV32IDZFH-NEXT:    feq.s a1, ft0, ft0
-; RV32IDZFH-NEXT:    bnez a1, .LBB5_5
-; RV32IDZFH-NEXT:  .LBB5_7: # %start
+; RV32IDZFH-NEXT:    bnez a1, .LBB6_5
+; RV32IDZFH-NEXT:  .LBB6_7: # %start
 ; RV32IDZFH-NEXT:    mv a0, zero
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_w_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
-; RV64IZFH-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV64IZFH-NEXT:    lui a0, %hi(.LCPI6_0)
+; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
 ; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
 ; RV64IZFH-NEXT:    lui a1, 524288
-; RV64IZFH-NEXT:    bnez a0, .LBB5_2
+; RV64IZFH-NEXT:    bnez a0, .LBB6_2
 ; RV64IZFH-NEXT:  # %bb.1: # %start
 ; RV64IZFH-NEXT:    lui a0, 524288
-; RV64IZFH-NEXT:    j .LBB5_3
-; RV64IZFH-NEXT:  .LBB5_2:
+; RV64IZFH-NEXT:    j .LBB6_3
+; RV64IZFH-NEXT:  .LBB6_2:
 ; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64IZFH-NEXT:  .LBB5_3: # %start
-; RV64IZFH-NEXT:    lui a2, %hi(.LCPI5_1)
-; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
+; RV64IZFH-NEXT:  .LBB6_3: # %start
+; RV64IZFH-NEXT:    lui a2, %hi(.LCPI6_1)
+; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
 ; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
-; RV64IZFH-NEXT:    bnez a2, .LBB5_6
+; RV64IZFH-NEXT:    bnez a2, .LBB6_6
 ; RV64IZFH-NEXT:  # %bb.4: # %start
 ; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IZFH-NEXT:    beqz a1, .LBB5_7
-; RV64IZFH-NEXT:  .LBB5_5: # %start
+; RV64IZFH-NEXT:    beqz a1, .LBB6_7
+; RV64IZFH-NEXT:  .LBB6_5: # %start
 ; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB5_6:
+; RV64IZFH-NEXT:  .LBB6_6:
 ; RV64IZFH-NEXT:    addiw a0, a1, -1
 ; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IZFH-NEXT:    bnez a1, .LBB5_5
-; RV64IZFH-NEXT:  .LBB5_7: # %start
+; RV64IZFH-NEXT:    bnez a1, .LBB6_5
+; RV64IZFH-NEXT:  .LBB6_7: # %start
 ; RV64IZFH-NEXT:    mv a0, zero
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
-; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
+; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI6_0)
+; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
 ; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
 ; RV64IDZFH-NEXT:    lui a1, 524288
-; RV64IDZFH-NEXT:    bnez a0, .LBB5_2
+; RV64IDZFH-NEXT:    bnez a0, .LBB6_2
 ; RV64IDZFH-NEXT:  # %bb.1: # %start
 ; RV64IDZFH-NEXT:    lui a0, 524288
-; RV64IDZFH-NEXT:    j .LBB5_3
-; RV64IDZFH-NEXT:  .LBB5_2:
+; RV64IDZFH-NEXT:    j .LBB6_3
+; RV64IDZFH-NEXT:  .LBB6_2:
 ; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64IDZFH-NEXT:  .LBB5_3: # %start
-; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI5_1)
-; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
+; RV64IDZFH-NEXT:  .LBB6_3: # %start
+; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI6_1)
+; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
 ; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
-; RV64IDZFH-NEXT:    bnez a2, .LBB5_6
+; RV64IDZFH-NEXT:    bnez a2, .LBB6_6
 ; RV64IDZFH-NEXT:  # %bb.4: # %start
 ; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IDZFH-NEXT:    beqz a1, .LBB5_7
-; RV64IDZFH-NEXT:  .LBB5_5: # %start
+; RV64IDZFH-NEXT:    beqz a1, .LBB6_7
+; RV64IDZFH-NEXT:  .LBB6_5: # %start
 ; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB5_6:
+; RV64IDZFH-NEXT:  .LBB6_6:
 ; RV64IDZFH-NEXT:    addiw a0, a1, -1
 ; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IDZFH-NEXT:    bnez a1, .LBB5_5
-; RV64IDZFH-NEXT:  .LBB5_7: # %start
+; RV64IDZFH-NEXT:    bnez a1, .LBB6_5
+; RV64IDZFH-NEXT:  .LBB6_7: # %start
 ; RV64IDZFH-NEXT:    mv a0, zero
 ; RV64IDZFH-NEXT:    ret
 start:
@@ -368,21 +417,21 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
 ; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IZFH-NEXT:    fmv.w.x ft1, zero
 ; RV32IZFH-NEXT:    fle.s a0, ft1, ft0
-; RV32IZFH-NEXT:    bnez a0, .LBB7_2
+; RV32IZFH-NEXT:    bnez a0, .LBB8_2
 ; RV32IZFH-NEXT:  # %bb.1: # %start
 ; RV32IZFH-NEXT:    mv a1, zero
-; RV32IZFH-NEXT:    j .LBB7_3
-; RV32IZFH-NEXT:  .LBB7_2:
+; RV32IZFH-NEXT:    j .LBB8_3
+; RV32IZFH-NEXT:  .LBB8_2:
 ; RV32IZFH-NEXT:    fcvt.wu.s a1, ft0, rtz
-; RV32IZFH-NEXT:  .LBB7_3: # %start
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
+; RV32IZFH-NEXT:  .LBB8_3: # %start
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI8_0)
+; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a0)
 ; RV32IZFH-NEXT:    flt.s a2, ft1, ft0
 ; RV32IZFH-NEXT:    addi a0, zero, -1
-; RV32IZFH-NEXT:    bnez a2, .LBB7_5
+; RV32IZFH-NEXT:    bnez a2, .LBB8_5
 ; RV32IZFH-NEXT:  # %bb.4: # %start
 ; RV32IZFH-NEXT:    mv a0, a1
-; RV32IZFH-NEXT:  .LBB7_5: # %start
+; RV32IZFH-NEXT:  .LBB8_5: # %start
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h_sat:
@@ -390,21 +439,21 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
 ; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IDZFH-NEXT:    fmv.w.x ft1, zero
 ; RV32IDZFH-NEXT:    fle.s a0, ft1, ft0
-; RV32IDZFH-NEXT:    bnez a0, .LBB7_2
+; RV32IDZFH-NEXT:    bnez a0, .LBB8_2
 ; RV32IDZFH-NEXT:  # %bb.1: # %start
 ; RV32IDZFH-NEXT:    mv a1, zero
-; RV32IDZFH-NEXT:    j .LBB7_3
-; RV32IDZFH-NEXT:  .LBB7_2:
+; RV32IDZFH-NEXT:    j .LBB8_3
+; RV32IDZFH-NEXT:  .LBB8_2:
 ; RV32IDZFH-NEXT:    fcvt.wu.s a1, ft0, rtz
-; RV32IDZFH-NEXT:  .LBB7_3: # %start
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
+; RV32IDZFH-NEXT:  .LBB8_3: # %start
+; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI8_0)
+; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a0)
 ; RV32IDZFH-NEXT:    flt.s a2, ft1, ft0
 ; RV32IDZFH-NEXT:    addi a0, zero, -1
-; RV32IDZFH-NEXT:    bnez a2, .LBB7_5
+; RV32IDZFH-NEXT:    bnez a2, .LBB8_5
 ; RV32IDZFH-NEXT:  # %bb.4: # %start
 ; RV32IDZFH-NEXT:    mv a0, a1
-; RV32IDZFH-NEXT:  .LBB7_5: # %start
+; RV32IDZFH-NEXT:  .LBB8_5: # %start
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_wu_h_sat:
@@ -412,21 +461,21 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
 ; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IZFH-NEXT:    fmv.w.x ft1, zero
 ; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
-; RV64IZFH-NEXT:    bnez a0, .LBB7_2
+; RV64IZFH-NEXT:    bnez a0, .LBB8_2
 ; RV64IZFH-NEXT:  # %bb.1: # %start
 ; RV64IZFH-NEXT:    mv a0, zero
-; RV64IZFH-NEXT:    j .LBB7_3
-; RV64IZFH-NEXT:  .LBB7_2:
+; RV64IZFH-NEXT:    j .LBB8_3
+; RV64IZFH-NEXT:  .LBB8_2:
 ; RV64IZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64IZFH-NEXT:  .LBB7_3: # %start
-; RV64IZFH-NEXT:    lui a1, %hi(.LCPI7_0)
-; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a1)
+; RV64IZFH-NEXT:  .LBB8_3: # %start
+; RV64IZFH-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a1)
 ; RV64IZFH-NEXT:    flt.s a1, ft1, ft0
-; RV64IZFH-NEXT:    beqz a1, .LBB7_5
+; RV64IZFH-NEXT:    beqz a1, .LBB8_5
 ; RV64IZFH-NEXT:  # %bb.4:
 ; RV64IZFH-NEXT:    addi a0, zero, -1
 ; RV64IZFH-NEXT:    srli a0, a0, 32
-; RV64IZFH-NEXT:  .LBB7_5: # %start
+; RV64IZFH-NEXT:  .LBB8_5: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h_sat:
@@ -434,21 +483,21 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
 ; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IDZFH-NEXT:    fmv.w.x ft1, zero
 ; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
-; RV64IDZFH-NEXT:    bnez a0, .LBB7_2
+; RV64IDZFH-NEXT:    bnez a0, .LBB8_2
 ; RV64IDZFH-NEXT:  # %bb.1: # %start
 ; RV64IDZFH-NEXT:    mv a0, zero
-; RV64IDZFH-NEXT:    j .LBB7_3
-; RV64IDZFH-NEXT:  .LBB7_2:
+; RV64IDZFH-NEXT:    j .LBB8_3
+; RV64IDZFH-NEXT:  .LBB8_2:
 ; RV64IDZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64IDZFH-NEXT:  .LBB7_3: # %start
-; RV64IDZFH-NEXT:    lui a1, %hi(.LCPI7_0)
-; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a1)
+; RV64IDZFH-NEXT:  .LBB8_3: # %start
+; RV64IDZFH-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a1)
 ; RV64IDZFH-NEXT:    flt.s a1, ft1, ft0
-; RV64IDZFH-NEXT:    beqz a1, .LBB7_5
+; RV64IDZFH-NEXT:    beqz a1, .LBB8_5
 ; RV64IDZFH-NEXT:  # %bb.4:
 ; RV64IDZFH-NEXT:    addi a0, zero, -1
 ; RV64IDZFH-NEXT:    srli a0, a0, 32
-; RV64IDZFH-NEXT:  .LBB7_5: # %start
+; RV64IDZFH-NEXT:  .LBB8_5: # %start
 ; RV64IDZFH-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
@@ -495,55 +544,55 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
 ; RV32IZFH-NEXT:    mv a2, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB9_2
+; RV32IZFH-NEXT:    bnez s0, .LBB10_2
 ; RV32IZFH-NEXT:  # %bb.1: # %start
 ; RV32IZFH-NEXT:    mv a2, zero
-; RV32IZFH-NEXT:  .LBB9_2: # %start
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI9_1)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
+; RV32IZFH-NEXT:  .LBB10_2: # %start
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI10_1)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a0)
 ; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
 ; RV32IZFH-NEXT:    addi a0, zero, -1
-; RV32IZFH-NEXT:    beqz a3, .LBB9_9
+; RV32IZFH-NEXT:    beqz a3, .LBB10_9
 ; RV32IZFH-NEXT:  # %bb.3: # %start
 ; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    beqz a2, .LBB9_10
-; RV32IZFH-NEXT:  .LBB9_4: # %start
+; RV32IZFH-NEXT:    beqz a2, .LBB10_10
+; RV32IZFH-NEXT:  .LBB10_4: # %start
 ; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB9_11
-; RV32IZFH-NEXT:  .LBB9_5: # %start
-; RV32IZFH-NEXT:    bnez a3, .LBB9_12
-; RV32IZFH-NEXT:  .LBB9_6: # %start
-; RV32IZFH-NEXT:    bnez a2, .LBB9_8
-; RV32IZFH-NEXT:  .LBB9_7: # %start
+; RV32IZFH-NEXT:    beqz s0, .LBB10_11
+; RV32IZFH-NEXT:  .LBB10_5: # %start
+; RV32IZFH-NEXT:    bnez a3, .LBB10_12
+; RV32IZFH-NEXT:  .LBB10_6: # %start
+; RV32IZFH-NEXT:    bnez a2, .LBB10_8
+; RV32IZFH-NEXT:  .LBB10_7: # %start
 ; RV32IZFH-NEXT:    mv a1, zero
-; RV32IZFH-NEXT:  .LBB9_8: # %start
+; RV32IZFH-NEXT:  .LBB10_8: # %start
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB9_9: # %start
+; RV32IZFH-NEXT:  .LBB10_9: # %start
 ; RV32IZFH-NEXT:    mv a0, a2
 ; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    bnez a2, .LBB9_4
-; RV32IZFH-NEXT:  .LBB9_10: # %start
+; RV32IZFH-NEXT:    bnez a2, .LBB10_4
+; RV32IZFH-NEXT:  .LBB10_10: # %start
 ; RV32IZFH-NEXT:    mv a0, zero
 ; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    bnez s0, .LBB9_5
-; RV32IZFH-NEXT:  .LBB9_11: # %start
+; RV32IZFH-NEXT:    bnez s0, .LBB10_5
+; RV32IZFH-NEXT:  .LBB10_11: # %start
 ; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    beqz a3, .LBB9_6
-; RV32IZFH-NEXT:  .LBB9_12:
+; RV32IZFH-NEXT:    beqz a3, .LBB10_6
+; RV32IZFH-NEXT:  .LBB10_12:
 ; RV32IZFH-NEXT:    addi a1, a4, -1
-; RV32IZFH-NEXT:    beqz a2, .LBB9_7
-; RV32IZFH-NEXT:    j .LBB9_8
+; RV32IZFH-NEXT:    beqz a2, .LBB10_7
+; RV32IZFH-NEXT:    j .LBB10_8
 ;
 ; RV32IDZFH-LABEL: fcvt_l_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
@@ -551,115 +600,115 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
+; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
 ; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IDZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IDZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IDZFH-NEXT:    call __fixsfdi@plt
 ; RV32IDZFH-NEXT:    mv a2, a0
-; RV32IDZFH-NEXT:    bnez s0, .LBB9_2
+; RV32IDZFH-NEXT:    bnez s0, .LBB10_2
 ; RV32IDZFH-NEXT:  # %bb.1: # %start
 ; RV32IDZFH-NEXT:    mv a2, zero
-; RV32IDZFH-NEXT:  .LBB9_2: # %start
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI9_1)
-; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
+; RV32IDZFH-NEXT:  .LBB10_2: # %start
+; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI10_1)
+; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a0)
 ; RV32IDZFH-NEXT:    flt.s a3, ft0, fs0
 ; RV32IDZFH-NEXT:    addi a0, zero, -1
-; RV32IDZFH-NEXT:    beqz a3, .LBB9_9
+; RV32IDZFH-NEXT:    beqz a3, .LBB10_9
 ; RV32IDZFH-NEXT:  # %bb.3: # %start
 ; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IDZFH-NEXT:    beqz a2, .LBB9_10
-; RV32IDZFH-NEXT:  .LBB9_4: # %start
+; RV32IDZFH-NEXT:    beqz a2, .LBB10_10
+; RV32IDZFH-NEXT:  .LBB10_4: # %start
 ; RV32IDZFH-NEXT:    lui a4, 524288
-; RV32IDZFH-NEXT:    beqz s0, .LBB9_11
-; RV32IDZFH-NEXT:  .LBB9_5: # %start
-; RV32IDZFH-NEXT:    bnez a3, .LBB9_12
-; RV32IDZFH-NEXT:  .LBB9_6: # %start
-; RV32IDZFH-NEXT:    bnez a2, .LBB9_8
-; RV32IDZFH-NEXT:  .LBB9_7: # %start
+; RV32IDZFH-NEXT:    beqz s0, .LBB10_11
+; RV32IDZFH-NEXT:  .LBB10_5: # %start
+; RV32IDZFH-NEXT:    bnez a3, .LBB10_12
+; RV32IDZFH-NEXT:  .LBB10_6: # %start
+; RV32IDZFH-NEXT:    bnez a2, .LBB10_8
+; RV32IDZFH-NEXT:  .LBB10_7: # %start
 ; RV32IDZFH-NEXT:    mv a1, zero
-; RV32IDZFH-NEXT:  .LBB9_8: # %start
+; RV32IDZFH-NEXT:  .LBB10_8: # %start
 ; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB9_9: # %start
+; RV32IDZFH-NEXT:  .LBB10_9: # %start
 ; RV32IDZFH-NEXT:    mv a0, a2
 ; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IDZFH-NEXT:    bnez a2, .LBB9_4
-; RV32IDZFH-NEXT:  .LBB9_10: # %start
+; RV32IDZFH-NEXT:    bnez a2, .LBB10_4
+; RV32IDZFH-NEXT:  .LBB10_10: # %start
 ; RV32IDZFH-NEXT:    mv a0, zero
 ; RV32IDZFH-NEXT:    lui a4, 524288
-; RV32IDZFH-NEXT:    bnez s0, .LBB9_5
-; RV32IDZFH-NEXT:  .LBB9_11: # %start
+; RV32IDZFH-NEXT:    bnez s0, .LBB10_5
+; RV32IDZFH-NEXT:  .LBB10_11: # %start
 ; RV32IDZFH-NEXT:    lui a1, 524288
-; RV32IDZFH-NEXT:    beqz a3, .LBB9_6
-; RV32IDZFH-NEXT:  .LBB9_12:
+; RV32IDZFH-NEXT:    beqz a3, .LBB10_6
+; RV32IDZFH-NEXT:  .LBB10_12:
 ; RV32IDZFH-NEXT:    addi a1, a4, -1
-; RV32IDZFH-NEXT:    beqz a2, .LBB9_7
-; RV32IDZFH-NEXT:    j .LBB9_8
+; RV32IDZFH-NEXT:    beqz a2, .LBB10_7
+; RV32IDZFH-NEXT:    j .LBB10_8
 ;
 ; RV64IZFH-LABEL: fcvt_l_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
-; RV64IZFH-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
+; RV64IZFH-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI10_0)(a0)
 ; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
 ; RV64IZFH-NEXT:    addi a1, zero, -1
-; RV64IZFH-NEXT:    bnez a0, .LBB9_2
+; RV64IZFH-NEXT:    bnez a0, .LBB10_2
 ; RV64IZFH-NEXT:  # %bb.1: # %start
 ; RV64IZFH-NEXT:    slli a0, a1, 63
-; RV64IZFH-NEXT:    j .LBB9_3
-; RV64IZFH-NEXT:  .LBB9_2:
+; RV64IZFH-NEXT:    j .LBB10_3
+; RV64IZFH-NEXT:  .LBB10_2:
 ; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64IZFH-NEXT:  .LBB9_3: # %start
-; RV64IZFH-NEXT:    lui a2, %hi(.LCPI9_1)
-; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI9_1)(a2)
+; RV64IZFH-NEXT:  .LBB10_3: # %start
+; RV64IZFH-NEXT:    lui a2, %hi(.LCPI10_1)
+; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI10_1)(a2)
 ; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
-; RV64IZFH-NEXT:    bnez a2, .LBB9_6
+; RV64IZFH-NEXT:    bnez a2, .LBB10_6
 ; RV64IZFH-NEXT:  # %bb.4: # %start
 ; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IZFH-NEXT:    beqz a1, .LBB9_7
-; RV64IZFH-NEXT:  .LBB9_5: # %start
+; RV64IZFH-NEXT:    beqz a1, .LBB10_7
+; RV64IZFH-NEXT:  .LBB10_5: # %start
 ; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB9_6:
+; RV64IZFH-NEXT:  .LBB10_6:
 ; RV64IZFH-NEXT:    srli a0, a1, 1
 ; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IZFH-NEXT:    bnez a1, .LBB9_5
-; RV64IZFH-NEXT:  .LBB9_7: # %start
+; RV64IZFH-NEXT:    bnez a1, .LBB10_5
+; RV64IZFH-NEXT:  .LBB10_7: # %start
 ; RV64IZFH-NEXT:    mv a0, zero
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_l_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
-; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
+; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI10_0)
+; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI10_0)(a0)
 ; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
 ; RV64IDZFH-NEXT:    addi a1, zero, -1
-; RV64IDZFH-NEXT:    bnez a0, .LBB9_2
+; RV64IDZFH-NEXT:    bnez a0, .LBB10_2
 ; RV64IDZFH-NEXT:  # %bb.1: # %start
 ; RV64IDZFH-NEXT:    slli a0, a1, 63
-; RV64IDZFH-NEXT:    j .LBB9_3
-; RV64IDZFH-NEXT:  .LBB9_2:
+; RV64IDZFH-NEXT:    j .LBB10_3
+; RV64IDZFH-NEXT:  .LBB10_2:
 ; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64IDZFH-NEXT:  .LBB9_3: # %start
-; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI9_1)
-; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI9_1)(a2)
+; RV64IDZFH-NEXT:  .LBB10_3: # %start
+; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI10_1)
+; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI10_1)(a2)
 ; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
-; RV64IDZFH-NEXT:    bnez a2, .LBB9_6
+; RV64IDZFH-NEXT:    bnez a2, .LBB10_6
 ; RV64IDZFH-NEXT:  # %bb.4: # %start
 ; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IDZFH-NEXT:    beqz a1, .LBB9_7
-; RV64IDZFH-NEXT:  .LBB9_5: # %start
+; RV64IDZFH-NEXT:    beqz a1, .LBB10_7
+; RV64IDZFH-NEXT:  .LBB10_5: # %start
 ; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB9_6:
+; RV64IDZFH-NEXT:  .LBB10_6:
 ; RV64IDZFH-NEXT:    srli a0, a1, 1
 ; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
-; RV64IDZFH-NEXT:    bnez a1, .LBB9_5
-; RV64IDZFH-NEXT:  .LBB9_7: # %start
+; RV64IDZFH-NEXT:    bnez a1, .LBB10_5
+; RV64IDZFH-NEXT:  .LBB10_7: # %start
 ; RV64IDZFH-NEXT:    mv a0, zero
 ; RV64IDZFH-NEXT:    ret
 start:
@@ -713,36 +762,36 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
 ; RV32IZFH-NEXT:    mv a3, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB11_2
+; RV32IZFH-NEXT:    bnez s0, .LBB12_2
 ; RV32IZFH-NEXT:  # %bb.1: # %start
 ; RV32IZFH-NEXT:    mv a3, zero
-; RV32IZFH-NEXT:  .LBB11_2: # %start
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI11_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
+; RV32IZFH-NEXT:  .LBB12_2: # %start
+; RV32IZFH-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
 ; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
 ; RV32IZFH-NEXT:    addi a2, zero, -1
 ; RV32IZFH-NEXT:    addi a0, zero, -1
-; RV32IZFH-NEXT:    beqz a4, .LBB11_7
+; RV32IZFH-NEXT:    beqz a4, .LBB12_7
 ; RV32IZFH-NEXT:  # %bb.3: # %start
-; RV32IZFH-NEXT:    beqz s0, .LBB11_8
-; RV32IZFH-NEXT:  .LBB11_4: # %start
-; RV32IZFH-NEXT:    bnez a4, .LBB11_6
-; RV32IZFH-NEXT:  .LBB11_5: # %start
+; RV32IZFH-NEXT:    beqz s0, .LBB12_8
+; RV32IZFH-NEXT:  .LBB12_4: # %start
+; RV32IZFH-NEXT:    bnez a4, .LBB12_6
+; RV32IZFH-NEXT:  .LBB12_5: # %start
 ; RV32IZFH-NEXT:    mv a2, a1
-; RV32IZFH-NEXT:  .LBB11_6: # %start
+; RV32IZFH-NEXT:  .LBB12_6: # %start
 ; RV32IZFH-NEXT:    mv a1, a2
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB11_7: # %start
+; RV32IZFH-NEXT:  .LBB12_7: # %start
 ; RV32IZFH-NEXT:    mv a0, a3
-; RV32IZFH-NEXT:    bnez s0, .LBB11_4
-; RV32IZFH-NEXT:  .LBB11_8: # %start
+; RV32IZFH-NEXT:    bnez s0, .LBB12_4
+; RV32IZFH-NEXT:  .LBB12_8: # %start
 ; RV32IZFH-NEXT:    mv a1, zero
-; RV32IZFH-NEXT:    beqz a4, .LBB11_5
-; RV32IZFH-NEXT:    j .LBB11_6
+; RV32IZFH-NEXT:    beqz a4, .LBB12_5
+; RV32IZFH-NEXT:    j .LBB12_6
 ;
 ; RV32IDZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
@@ -756,57 +805,57 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
 ; RV32IDZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IDZFH-NEXT:    call __fixunssfdi@plt
 ; RV32IDZFH-NEXT:    mv a3, a0
-; RV32IDZFH-NEXT:    bnez s0, .LBB11_2
+; RV32IDZFH-NEXT:    bnez s0, .LBB12_2
 ; RV32IDZFH-NEXT:  # %bb.1: # %start
 ; RV32IDZFH-NEXT:    mv a3, zero
-; RV32IDZFH-NEXT:  .LBB11_2: # %start
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI11_0)
-; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
+; RV32IDZFH-NEXT:  .LBB12_2: # %start
+; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
 ; RV32IDZFH-NEXT:    flt.s a4, ft0, fs0
 ; RV32IDZFH-NEXT:    addi a2, zero, -1
 ; RV32IDZFH-NEXT:    addi a0, zero, -1
-; RV32IDZFH-NEXT:    beqz a4, .LBB11_7
+; RV32IDZFH-NEXT:    beqz a4, .LBB12_7
 ; RV32IDZFH-NEXT:  # %bb.3: # %start
-; RV32IDZFH-NEXT:    beqz s0, .LBB11_8
-; RV32IDZFH-NEXT:  .LBB11_4: # %start
-; RV32IDZFH-NEXT:    bnez a4, .LBB11_6
-; RV32IDZFH-NEXT:  .LBB11_5: # %start
+; RV32IDZFH-NEXT:    beqz s0, .LBB12_8
+; RV32IDZFH-NEXT:  .LBB12_4: # %start
+; RV32IDZFH-NEXT:    bnez a4, .LBB12_6
+; RV32IDZFH-NEXT:  .LBB12_5: # %start
 ; RV32IDZFH-NEXT:    mv a2, a1
-; RV32IDZFH-NEXT:  .LBB11_6: # %start
+; RV32IDZFH-NEXT:  .LBB12_6: # %start
 ; RV32IDZFH-NEXT:    mv a1, a2
 ; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB11_7: # %start
+; RV32IDZFH-NEXT:  .LBB12_7: # %start
 ; RV32IDZFH-NEXT:    mv a0, a3
-; RV32IDZFH-NEXT:    bnez s0, .LBB11_4
-; RV32IDZFH-NEXT:  .LBB11_8: # %start
+; RV32IDZFH-NEXT:    bnez s0, .LBB12_4
+; RV32IDZFH-NEXT:  .LBB12_8: # %start
 ; RV32IDZFH-NEXT:    mv a1, zero
-; RV32IDZFH-NEXT:    beqz a4, .LBB11_5
-; RV32IDZFH-NEXT:    j .LBB11_6
+; RV32IDZFH-NEXT:    beqz a4, .LBB12_5
+; RV32IDZFH-NEXT:    j .LBB12_6
 ;
 ; RV64IZFH-LABEL: fcvt_lu_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IZFH-NEXT:    fmv.w.x ft1, zero
 ; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
-; RV64IZFH-NEXT:    bnez a0, .LBB11_2
+; RV64IZFH-NEXT:    bnez a0, .LBB12_2
 ; RV64IZFH-NEXT:  # %bb.1: # %start
 ; RV64IZFH-NEXT:    mv a1, zero
-; RV64IZFH-NEXT:    j .LBB11_3
-; RV64IZFH-NEXT:  .LBB11_2:
+; RV64IZFH-NEXT:    j .LBB12_3
+; RV64IZFH-NEXT:  .LBB12_2:
 ; RV64IZFH-NEXT:    fcvt.lu.s a1, ft0, rtz
-; RV64IZFH-NEXT:  .LBB11_3: # %start
-; RV64IZFH-NEXT:    lui a0, %hi(.LCPI11_0)
-; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
+; RV64IZFH-NEXT:  .LBB12_3: # %start
+; RV64IZFH-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI12_0)(a0)
 ; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
 ; RV64IZFH-NEXT:    addi a0, zero, -1
-; RV64IZFH-NEXT:    bnez a2, .LBB11_5
+; RV64IZFH-NEXT:    bnez a2, .LBB12_5
 ; RV64IZFH-NEXT:  # %bb.4: # %start
 ; RV64IZFH-NEXT:    mv a0, a1
-; RV64IZFH-NEXT:  .LBB11_5: # %start
+; RV64IZFH-NEXT:  .LBB12_5: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_lu_h_sat:
@@ -814,21 +863,21 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
 ; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IDZFH-NEXT:    fmv.w.x ft1, zero
 ; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
-; RV64IDZFH-NEXT:    bnez a0, .LBB11_2
+; RV64IDZFH-NEXT:    bnez a0, .LBB12_2
 ; RV64IDZFH-NEXT:  # %bb.1: # %start
 ; RV64IDZFH-NEXT:    mv a1, zero
-; RV64IDZFH-NEXT:    j .LBB11_3
-; RV64IDZFH-NEXT:  .LBB11_2:
+; RV64IDZFH-NEXT:    j .LBB12_3
+; RV64IDZFH-NEXT:  .LBB12_2:
 ; RV64IDZFH-NEXT:    fcvt.lu.s a1, ft0, rtz
-; RV64IDZFH-NEXT:  .LBB11_3: # %start
-; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI11_0)
-; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
+; RV64IDZFH-NEXT:  .LBB12_3: # %start
+; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI12_0)
+; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI12_0)(a0)
 ; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
 ; RV64IDZFH-NEXT:    addi a0, zero, -1
-; RV64IDZFH-NEXT:    bnez a2, .LBB11_5
+; RV64IDZFH-NEXT:    bnez a2, .LBB12_5
 ; RV64IDZFH-NEXT:  # %bb.4: # %start
 ; RV64IDZFH-NEXT:    mv a0, a1
-; RV64IDZFH-NEXT:  .LBB11_5: # %start
+; RV64IDZFH-NEXT:  .LBB12_5: # %start
 ; RV64IDZFH-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)