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[AMDGPU] Temporarily change constant address space from 4 to 2

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Our final address space mapping is to let constant address space to be 4 to match nvptx.
However for now we will make it 2 to avoid unnecessary work in FE/BE/devlib
about intrinsics returning constant pointers.

Differential Revision: https://reviews.llvm.org/D31770

llvm-svn: 299690
This commit is contained in:
Yaxun Liu 2017-04-06 19:17:32 +00:00
parent 24733be9ad
commit 3bf809b0e4
4 changed files with 8 additions and 10 deletions
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2
lib/Target/AMDGPU/AMDGPU.h
View File

@ -154,7 +154,6 @@ enum TargetIndex {
struct AMDGPUAS {
// The following address space values depend on the triple environment.
unsigned PRIVATE_ADDRESS; ///< Address space for private memory.
unsigned CONSTANT_ADDRESS; ///< Address space for constant memory (VTX2)
unsigned FLAT_ADDRESS; ///< Address space for flat memory.
unsigned REGION_ADDRESS; ///< Address space for region memory.
@ -162,6 +161,7 @@ struct AMDGPUAS {
const static unsigned MAX_COMMON_ADDRESS = 5;
const static unsigned GLOBAL_ADDRESS = 1; ///< Address space for global memory (RAT0, VTX0).
const static unsigned CONSTANT_ADDRESS = 2; ///< Address space for constant memory (VTX2)
const static unsigned LOCAL_ADDRESS = 3; ///< Address space for local memory.
const static unsigned PARAM_D_ADDRESS = 6; ///< Address space for direct addressible parameter memory (CONST0)
const static unsigned PARAM_I_ADDRESS = 7; ///< Address space for indirect addressible parameter memory (VTX1)

10
lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
View File

@ -52,20 +52,20 @@ AMDGPUAAResult::ASAliasRulesTy::ASAliasRulesTy(AMDGPUAS AS_, Triple::ArchType Ar
/* Region */ {NoAlias , NoAlias , NoAlias , NoAlias , MayAlias, MayAlias}
};
static const AliasResult ASAliasRulesGenIsZero[6][6] = {
/* Flat Global Region Group Constant Private */
/* Flat Global Constant Group Region Private */
/* Flat */ {MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias},
/* Global */ {MayAlias, MayAlias, NoAlias , NoAlias , NoAlias , NoAlias},
/* Region */ {NoAlias , NoAlias , MayAlias, NoAlias, NoAlias , MayAlias},
/* Constant */ {MayAlias, NoAlias , MayAlias, NoAlias , NoAlias, NoAlias},
/* Group */ {MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , NoAlias},
/* Constant */ {MayAlias, NoAlias , NoAlias , NoAlias , MayAlias, NoAlias},
/* Region */ {MayAlias, NoAlias , NoAlias , NoAlias, MayAlias, NoAlias},
/* Private */ {MayAlias, NoAlias , NoAlias , NoAlias , NoAlias , MayAlias}
};
assert(AS.MAX_COMMON_ADDRESS <= 5);
if (AS.FLAT_ADDRESS == 0) {
assert(AS.GLOBAL_ADDRESS == 1 &&
AS.REGION_ADDRESS == 2 &&
AS.REGION_ADDRESS == 4 &&
AS.LOCAL_ADDRESS == 3 &&
AS.CONSTANT_ADDRESS == 4 &&
AS.CONSTANT_ADDRESS == 2 &&
AS.PRIVATE_ADDRESS == 5);
ASAliasRules = &ASAliasRulesGenIsZero;
} else {

2
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -212,7 +212,7 @@ static StringRef computeDataLayout(const Triple &TT) {
// flat.
if (TT.getEnvironmentName() == "amdgiz" ||
TT.getEnvironmentName() == "amdgizcl")
return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"

4
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
View File

@ -772,13 +772,11 @@ AMDGPUAS getAMDGPUAS(Triple T) {
AMDGPUAS AS;
if (Env == "amdgiz" || Env == "amdgizcl") {
AS.FLAT_ADDRESS = 0;
AS.CONSTANT_ADDRESS = 4;
AS.PRIVATE_ADDRESS = 5;
AS.REGION_ADDRESS = 2;
AS.REGION_ADDRESS = 4;
}
else {
AS.FLAT_ADDRESS = 4;
AS.CONSTANT_ADDRESS = 2;
AS.PRIVATE_ADDRESS = 0;
AS.REGION_ADDRESS = 5;
}