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[DAGCombine] Improve select (not Cond), N1, N2 -> select Cond, N2, N1 fold

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Move the x86 combine from D58974 into the DAGCombine VSELECT code and update the SELECT version to use the isBooleanFlip helper as well.

Requested by @spatel on D59006

llvm-svn: 355533
This commit is contained in:
Simon Pilgrim 2019-03-06 18:52:52 +00:00
parent 04ab7d8c4f
commit 3c05b470dc
2 changed files with 15 additions and 15 deletions
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24
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2399,9 +2399,12 @@ static SDValue flipBoolean(SDValue V, const SDLoc &DL, EVT VT,
}
static bool isBooleanFlip(SDValue V, EVT VT, const TargetLowering &TLI) {
if (V.getOpcode() != ISD::XOR) return false;
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V.getOperand(1));
if (!Const) return false;
if (V.getOpcode() != ISD::XOR)
return false;
ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
if (!Const)
return false;
switch(TLI.getBooleanContents(VT)) {
case TargetLowering::ZeroOrOneBooleanContent:
@ -7640,11 +7643,9 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
}
}
if (VT0 == MVT::i1) {
// select (not Cond), N1, N2 -> select Cond, N2, N1
if (isBitwiseNot(N0))
return DAG.getNode(ISD::SELECT, DL, VT, N0->getOperand(0), N2, N1);
}
// select (not Cond), N1, N2 -> select Cond, N2, N1
if (isBooleanFlip(N0, VT0, TLI))
return DAG.getSelect(DL, VT, N0.getOperand(0), N2, N1);
// Fold selects based on a setcc into other things, such as min/max/abs.
if (N0.getOpcode() == ISD::SETCC) {
@ -8117,11 +8118,17 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
EVT VT = N->getValueType(0);
EVT VT0 = N0.getValueType();
SDLoc DL(N);
if (SDValue V = DAG.simplifySelect(N0, N1, N2))
return V;
// vselect (not Cond), N1, N2 -> vselect Cond, N2, N1
if (isBooleanFlip(N0, VT0, TLI))
return DAG.getSelect(DL, VT, N0.getOperand(0), N2, N1);
// Canonicalize integer abs.
// vselect (setg[te] X, 0), X, -X ->
// vselect (setgt X, -1), X, -X ->
@ -8161,7 +8168,6 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
// This is OK if we don't care about what happens if either operand is a
// NaN.
//
EVT VT = N->getValueType(0);
if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(
DAG, N0.getOperand(0), N0.getOperand(1), TLI)) {
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -34684,12 +34684,6 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
return DAG.getVectorShuffle(VT, DL, LHS, RHS, Mask);
}
// Commute LHS/RHS if the Cond has been XOR'd.
// TODO: Move this to DAGCombine.
if (CondVT.getScalarSizeInBits() == VT.getScalarSizeInBits() &&
isBitwiseNot(Cond))
return DAG.getNode(N->getOpcode(), DL, VT, Cond.getOperand(0), RHS, LHS);
// If we have SSE[12] support, try to form min/max nodes. SSE min/max
// instructions match the semantics of the common C idiom x<y?x:y but not
// x<=y?x:y, because of how they handle negative zero (which can be