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[AArch64][SVE] Add patterns for unpredicated load/store to frame-indices.
This patch also fixes up a number of cases in DAGCombine and SelectionDAGBuilder where the size of a scalable vector is used in a fixed-width context (thus triggering an assertion failure). Reviewers: efriedma, c-rhodes, rovka, cameron.mcinally Reviewed By: efriedma Tags: #llvm Differential Revision: https://reviews.llvm.org/D71215
This commit is contained in:
Sander de Smalen
parent
1c282f08c9
commit
3c233e1b36
@ -19,6 +19,7 @@
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#include "llvm/ADT/Optional.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/Support/TypeSize.h"
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namespace llvm {
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@ -240,6 +241,12 @@ public:
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return getForArgument(Call, ArgIdx, &TLI);
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}
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// Return the exact size if the exact size is known at compiletime,
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// otherwise return MemoryLocation::UnknownSize.
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static uint64_t getSizeOrUnknown(const TypeSize &T) {
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return T.isScalable() ? UnknownSize : T.getFixedSize();
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}
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explicit MemoryLocation(const Value *Ptr = nullptr,
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LocationSize Size = LocationSize::unknown(),
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const AAMDNodes &AATags = AAMDNodes())
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@ -140,7 +140,9 @@ bool llvm::isDereferenceableAndAlignedPointer(const Value *V, Type *Ty,
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const DataLayout &DL,
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const Instruction *CtxI,
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const DominatorTree *DT) {
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if (!Ty->isSized())
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// For unsized types or scalable vectors we don't know exactly how many bytes
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// are dereferenced, so bail out.
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if (!Ty->isSized() || (Ty->isVectorTy() && Ty->getVectorIsScalable()))
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return false;
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// When dereferenceability information is provided by a dereferenceable
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@ -6809,6 +6809,14 @@ static bool splitMergedValStore(StoreInst &SI, const DataLayout &DL,
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const TargetLowering &TLI) {
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// Handle simple but common cases only.
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Type *StoreType = SI.getValueOperand()->getType();
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// The code below assumes shifting a value by <number of bits>,
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// whereas scalable vectors would have to be shifted by
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// <2log(vscale) + number of bits> in order to store the
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// low/high parts. Bailing out for now.
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if (StoreType->isVectorTy() && StoreType->getVectorIsScalable())
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return false;
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if (!DL.typeSizeEqualsStoreSize(StoreType) ||
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DL.getTypeSizeInBits(StoreType) == 0)
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return false;
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@ -15738,7 +15738,14 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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if (OptLevel == CodeGenOpt::None || !EnableStoreMerging)
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return false;
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// TODO: Extend this function to merge stores of scalable vectors.
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// (i.e. two <vscale x 8 x i8> stores can be merged to one <vscale x 16 x i8>
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// store since we know <vscale x 16 x i8> is exactly twice as large as
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// <vscale x 8 x i8>). Until then, bail out for scalable vectors.
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EVT MemVT = St->getMemoryVT();
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if (MemVT.isScalableVector())
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return false;
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int64_t ElementSizeBytes = MemVT.getStoreSize();
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unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1;
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@ -20842,9 +20849,11 @@ bool DAGCombiner::isAlias(SDNode *Op0, SDNode *Op1) const {
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: (LSN->getAddressingMode() == ISD::PRE_DEC)
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? -1 * C->getSExtValue()
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: 0;
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uint64_t Size =
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MemoryLocation::getSizeOrUnknown(LSN->getMemoryVT().getStoreSize());
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return {LSN->isVolatile(), LSN->isAtomic(), LSN->getBasePtr(),
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Offset /*base offset*/,
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Optional<int64_t>(LSN->getMemoryVT().getStoreSize()),
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Optional<int64_t>(Size),
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LSN->getMemOperand()};
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}
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if (const auto *LN = cast<LifetimeSDNode>(N))
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@ -21124,6 +21133,12 @@ bool DAGCombiner::parallelizeChainedStores(StoreSDNode *St) {
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if (BasePtr.getBase().isUndef())
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return false;
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// BaseIndexOffset assumes that offsets are fixed-size, which
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// is not valid for scalable vectors where the offsets are
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// scaled by `vscale`, so bail out early.
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if (St->getMemoryVT().isScalableVector())
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return false;
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// Add ST's interval.
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Intervals.insert(0, (St->getMemoryVT().getSizeInBits() + 7) / 8, Unit);
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@ -6824,9 +6824,10 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
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if (PtrInfo.V.isNull())
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PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
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uint64_t Size = MemoryLocation::getSizeOrUnknown(MemVT.getStoreSize());
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MachineFunction &MF = getMachineFunction();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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PtrInfo, MMOFlags, MemVT.getStoreSize(), Alignment, AAInfo, Ranges);
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PtrInfo, MMOFlags, Size, Alignment, AAInfo, Ranges);
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return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
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}
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@ -6946,8 +6947,10 @@ SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,
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PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr);
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MachineFunction &MF = getMachineFunction();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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PtrInfo, MMOFlags, Val.getValueType().getStoreSize(), Alignment, AAInfo);
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uint64_t Size =
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MemoryLocation::getSizeOrUnknown(Val.getValueType().getStoreSize());
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
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return getStore(Chain, dl, Val, Ptr, MMO);
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}
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@ -220,6 +220,8 @@ public:
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void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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bool SelectAddrModeFrameIndexSVE(SDValue N, SDValue &Base, SDValue &OffImm);
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void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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@ -1374,6 +1376,23 @@ void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
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ReplaceNode(N, St);
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}
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bool AArch64DAGToDAGISel::SelectAddrModeFrameIndexSVE(SDValue N, SDValue &Base,
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SDValue &OffImm) {
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SDLoc dl(N);
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const DataLayout &DL = CurDAG->getDataLayout();
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const TargetLowering *TLI = getTargetLowering();
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// Try to match it for the frame address
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if (auto FINode = dyn_cast<FrameIndexSDNode>(N)) {
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int FI = FINode->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
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OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
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return true;
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}
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return false;
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}
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void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
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unsigned Opc) {
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SDLoc dl(N);
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@ -9458,6 +9458,10 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
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if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
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return false;
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// FIXME: Update this method to support scalable addressing modes.
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if (Ty->isVectorTy() && Ty->getVectorIsScalable())
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return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale;
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// check reg + imm case:
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// i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
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uint64_t NumBytes = 0;
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@ -349,6 +349,8 @@ def simm7s16 : Operand<i32> {
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let PrintMethod = "printImmScale<16>";
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}
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def am_sve_fi : ComplexPattern<i64, 2, "SelectAddrModeFrameIndexSVE", []>;
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def am_indexed7s8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S8", []>;
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def am_indexed7s16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S16", []>;
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def am_indexed7s32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S32", []>;
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@ -1691,6 +1691,8 @@ unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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case AArch64::STRSui:
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case AArch64::STRDui:
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case AArch64::STRQui:
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case AArch64::LDR_PXI:
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case AArch64::STR_PXI:
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if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
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MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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@ -1803,9 +1805,19 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
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case AArch64::STNPSi:
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case AArch64::LDG:
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case AArch64::STGPi:
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case AArch64::LD1B_IMM:
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case AArch64::LD1H_IMM:
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case AArch64::LD1W_IMM:
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case AArch64::LD1D_IMM:
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case AArch64::ST1B_IMM:
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case AArch64::ST1H_IMM:
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case AArch64::ST1W_IMM:
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case AArch64::ST1D_IMM:
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return 3;
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case AArch64::ADDG:
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case AArch64::STGOffset:
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case AArch64::LDR_PXI:
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case AArch64::STR_PXI:
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return 2;
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}
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}
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@ -2056,6 +2068,7 @@ AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const {
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bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, unsigned &Scale,
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unsigned &Width, int64_t &MinOffset,
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int64_t &MaxOffset) {
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const unsigned SVEMaxBytesPerVector = AArch64::SVEMaxBitsPerVector / 8;
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switch (Opcode) {
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// Not a memory operation or something we want to handle.
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default:
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@ -2220,16 +2233,33 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, unsigned &Scale,
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break;
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case AArch64::LDR_PXI:
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case AArch64::STR_PXI:
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Scale = Width = 2;
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Scale = 2;
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Width = SVEMaxBytesPerVector / 8;
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MinOffset = -256;
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MaxOffset = 255;
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break;
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case AArch64::LDR_ZXI:
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case AArch64::STR_ZXI:
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Scale = Width = 16;
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Scale = 16;
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Width = SVEMaxBytesPerVector;
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MinOffset = -256;
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MaxOffset = 255;
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break;
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case AArch64::LD1B_IMM:
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case AArch64::LD1H_IMM:
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case AArch64::LD1W_IMM:
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case AArch64::LD1D_IMM:
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case AArch64::ST1B_IMM:
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case AArch64::ST1H_IMM:
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case AArch64::ST1W_IMM:
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case AArch64::ST1D_IMM:
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// A full vectors worth of data
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// Width = mbytes * elements
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Scale = 16;
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Width = SVEMaxBytesPerVector;
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MinOffset = -8;
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MaxOffset = 7;
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break;
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case AArch64::ST2GOffset:
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case AArch64::STZ2GOffset:
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Scale = 16;
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@ -3433,6 +3463,14 @@ static bool isSVEScaledImmInstruction(unsigned Opcode) {
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case AArch64::STR_ZXI:
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case AArch64::LDR_PXI:
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case AArch64::STR_PXI:
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case AArch64::LD1B_IMM:
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case AArch64::LD1H_IMM:
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case AArch64::LD1W_IMM:
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case AArch64::LD1D_IMM:
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case AArch64::ST1B_IMM:
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case AArch64::ST1H_IMM:
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case AArch64::ST1W_IMM:
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case AArch64::ST1D_IMM:
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return true;
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default:
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return false;
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@ -1261,6 +1261,52 @@ let Predicates = [HasSVE] in {
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defm : pred_store<nxv4i32, nxv4i1, non_temporal_store, STNT1W_ZRI>;
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defm : pred_store<nxv2i64, nxv2i1, non_temporal_store, STNT1D_ZRI>;
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multiclass unpred_store<ValueType Ty, Instruction RegImmInst, Instruction PTrue> {
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def _fi : Pat<(store (Ty ZPR:$val), (am_sve_fi GPR64sp:$base, simm4s1:$offset)),
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(RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
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}
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defm Pat_ST1B : unpred_store<nxv16i8, ST1B_IMM, PTRUE_B>;
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defm Pat_ST1H : unpred_store<nxv8i16, ST1H_IMM, PTRUE_H>;
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defm Pat_ST1W : unpred_store<nxv4i32, ST1W_IMM, PTRUE_S>;
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defm Pat_ST1D : unpred_store<nxv2i64, ST1D_IMM, PTRUE_D>;
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defm Pat_ST1H_float16: unpred_store<nxv8f16, ST1H_IMM, PTRUE_H>;
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defm Pat_ST1W_float : unpred_store<nxv4f32, ST1W_IMM, PTRUE_S>;
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defm Pat_ST1D_double : unpred_store<nxv2f64, ST1D_IMM, PTRUE_D>;
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multiclass unpred_load<ValueType Ty, Instruction RegImmInst, Instruction PTrue> {
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def _fi : Pat<(Ty (load (am_sve_fi GPR64sp:$base, simm4s1:$offset))),
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(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
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}
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defm Pat_LD1B : unpred_load<nxv16i8, LD1B_IMM, PTRUE_B>;
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defm Pat_LD1H : unpred_load<nxv8i16, LD1H_IMM, PTRUE_H>;
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defm Pat_LD1W : unpred_load<nxv4i32, LD1W_IMM, PTRUE_S>;
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defm Pat_LD1D : unpred_load<nxv2i64, LD1D_IMM, PTRUE_D>;
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defm Pat_LD1H_float16: unpred_load<nxv8f16, LD1H_IMM, PTRUE_H>;
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defm Pat_LD1W_float : unpred_load<nxv4f32, LD1W_IMM, PTRUE_S>;
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defm Pat_LD1D_double : unpred_load<nxv2f64, LD1D_IMM, PTRUE_D>;
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multiclass unpred_store_predicate<ValueType Ty, Instruction Store> {
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def _fi : Pat<(store (Ty PPR:$val), (am_sve_fi GPR64sp:$base, simm9:$offset)),
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(Store PPR:$val, GPR64sp:$base, simm9:$offset)>;
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}
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defm Pat_Store_P16 : unpred_store_predicate<nxv16i1, STR_PXI>;
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defm Pat_Store_P8 : unpred_store_predicate<nxv8i1, STR_PXI>;
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defm Pat_Store_P4 : unpred_store_predicate<nxv4i1, STR_PXI>;
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defm Pat_Store_P2 : unpred_store_predicate<nxv2i1, STR_PXI>;
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multiclass unpred_load_predicate<ValueType Ty, Instruction Load> {
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def _fi : Pat<(Ty (load (am_sve_fi GPR64sp:$base, simm9:$offset))),
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(Load GPR64sp:$base, simm9:$offset)>;
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}
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defm Pat_Load_P16 : unpred_load_predicate<nxv16i1, LDR_PXI>;
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defm Pat_Load_P8 : unpred_load_predicate<nxv8i1, LDR_PXI>;
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defm Pat_Load_P4 : unpred_load_predicate<nxv4i1, LDR_PXI>;
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defm Pat_Load_P2 : unpred_load_predicate<nxv2i1, LDR_PXI>;
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multiclass ldnf1<Instruction I, ValueType Ty, SDPatternOperator Load, ValueType PredTy, ValueType MemVT> {
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// base
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def : Pat<(Ty (Load (PredTy PPR:$gp), GPR64:$base, MemVT)),
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@ -658,6 +658,7 @@ namespace AArch64 {
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// in index i*P of a <n x (M*P) x t> vector. The other elements of the
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// <n x (M*P) x t> vector (such as index 1) are undefined.
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static constexpr unsigned SVEBitsPerBlock = 128;
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static constexpr unsigned SVEMaxBitsPerVector = 2048;
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const unsigned NeonBitsPerVector = 128;
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} // end namespace AArch64
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} // end namespace llvm
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189
test/CodeGen/AArch64/spillfill-sve.ll
Normal file
189
test/CodeGen/AArch64/spillfill-sve.ll
Normal file
@ -0,0 +1,189 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve < %s | FileCheck %s
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; This file checks that unpredicated load/store instructions to locals
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; use the right instructions and offsets.
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; Data fills
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define void @fill_nxv16i8() {
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; CHECK-LABEL: fill_nxv16i8
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; CHECK-DAG: ld1b { z{{[01]}}.b }, p0/z, [sp]
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; CHECK-DAG: ld1b { z{{[01]}}.b }, p0/z, [sp, #1, mul vl]
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%local0 = alloca <vscale x 16 x i8>
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%local1 = alloca <vscale x 16 x i8>
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1
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ret void
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}
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define void @fill_nxv8i16() {
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; CHECK-LABEL: fill_nxv8i16
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; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp]
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; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp, #1, mul vl]
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%local0 = alloca <vscale x 8 x i16>
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%local1 = alloca <vscale x 8 x i16>
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load volatile <vscale x 8 x i16>, <vscale x 8 x i16>* %local0
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load volatile <vscale x 8 x i16>, <vscale x 8 x i16>* %local1
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ret void
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}
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define void @fill_nxv4i32() {
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; CHECK-LABEL: fill_nxv4i32
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; CHECK-DAG: ld1w { z{{[01]}}.s }, p0/z, [sp]
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; CHECK-DAG: ld1w { z{{[01]}}.s }, p0/z, [sp, #1, mul vl]
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%local0 = alloca <vscale x 4 x i32>
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%local1 = alloca <vscale x 4 x i32>
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load volatile <vscale x 4 x i32>, <vscale x 4 x i32>* %local0
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load volatile <vscale x 4 x i32>, <vscale x 4 x i32>* %local1
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ret void
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}
|
||||
|
||||
define void @fill_nxv2i64() {
|
||||
; CHECK-LABEL: fill_nxv2i64
|
||||
; CHECK-DAG: ld1d { z{{[01]}}.d }, p0/z, [sp]
|
||||
; CHECK-DAG: ld1d { z{{[01]}}.d }, p0/z, [sp, #1, mul vl]
|
||||
%local0 = alloca <vscale x 2 x i64>
|
||||
%local1 = alloca <vscale x 2 x i64>
|
||||
load volatile <vscale x 2 x i64>, <vscale x 2 x i64>* %local0
|
||||
load volatile <vscale x 2 x i64>, <vscale x 2 x i64>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; Data spills
|
||||
|
||||
define void @spill_nxv16i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1) {
|
||||
; CHECK-LABEL: spill_nxv16i8
|
||||
; CHECK-DAG: st1b { z{{[01]}}.b }, p0, [sp]
|
||||
; CHECK-DAG: st1b { z{{[01]}}.b }, p0, [sp, #1, mul vl]
|
||||
%local0 = alloca <vscale x 16 x i8>
|
||||
%local1 = alloca <vscale x 16 x i8>
|
||||
store volatile <vscale x 16 x i8> %v0, <vscale x 16 x i8>* %local0
|
||||
store volatile <vscale x 16 x i8> %v1, <vscale x 16 x i8>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @spill_nxv8i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1) {
|
||||
; CHECK-LABEL: spill_nxv8i16
|
||||
; CHECK-DAG: st1h { z{{[01]}}.h }, p0, [sp]
|
||||
; CHECK-DAG: st1h { z{{[01]}}.h }, p0, [sp, #1, mul vl]
|
||||
%local0 = alloca <vscale x 8 x i16>
|
||||
%local1 = alloca <vscale x 8 x i16>
|
||||
store volatile <vscale x 8 x i16> %v0, <vscale x 8 x i16>* %local0
|
||||
store volatile <vscale x 8 x i16> %v1, <vscale x 8 x i16>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @spill_nxv4i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1) {
|
||||
; CHECK-LABEL: spill_nxv4i32
|
||||
; CHECK-DAG: st1w { z{{[01]}}.s }, p0, [sp]
|
||||
; CHECK-DAG: st1w { z{{[01]}}.s }, p0, [sp, #1, mul vl]
|
||||
%local0 = alloca <vscale x 4 x i32>
|
||||
%local1 = alloca <vscale x 4 x i32>
|
||||
store volatile <vscale x 4 x i32> %v0, <vscale x 4 x i32>* %local0
|
||||
store volatile <vscale x 4 x i32> %v1, <vscale x 4 x i32>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @spill_nxv2i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1) {
|
||||
; CHECK-LABEL: spill_nxv2i64
|
||||
; CHECK-DAG: st1d { z{{[01]}}.d }, p0, [sp]
|
||||
; CHECK-DAG: st1d { z{{[01]}}.d }, p0, [sp, #1, mul vl]
|
||||
%local0 = alloca <vscale x 2 x i64>
|
||||
%local1 = alloca <vscale x 2 x i64>
|
||||
store volatile <vscale x 2 x i64> %v0, <vscale x 2 x i64>* %local0
|
||||
store volatile <vscale x 2 x i64> %v1, <vscale x 2 x i64>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
; Predicate fills
|
||||
|
||||
define void @fill_nxv16i1() {
|
||||
; CHECK-LABEL: fill_nxv16i1
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp, #8, mul vl]
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp]
|
||||
%local0 = alloca <vscale x 16 x i1>
|
||||
%local1 = alloca <vscale x 16 x i1>
|
||||
load volatile <vscale x 16 x i1>, <vscale x 16 x i1>* %local0
|
||||
load volatile <vscale x 16 x i1>, <vscale x 16 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fill_nxv8i1() {
|
||||
; CHECK-LABEL: fill_nxv8i1
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp, #4, mul vl]
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp]
|
||||
%local0 = alloca <vscale x 8 x i1>
|
||||
%local1 = alloca <vscale x 8 x i1>
|
||||
load volatile <vscale x 8 x i1>, <vscale x 8 x i1>* %local0
|
||||
load volatile <vscale x 8 x i1>, <vscale x 8 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fill_nxv4i1() {
|
||||
; CHECK-LABEL: fill_nxv4i1
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp, #6, mul vl]
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp, #4, mul vl]
|
||||
%local0 = alloca <vscale x 4 x i1>
|
||||
%local1 = alloca <vscale x 4 x i1>
|
||||
load volatile <vscale x 4 x i1>, <vscale x 4 x i1>* %local0
|
||||
load volatile <vscale x 4 x i1>, <vscale x 4 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fill_nxv2i1() {
|
||||
; CHECK-LABEL: fill_nxv2i1
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp, #7, mul vl]
|
||||
; CHECK-DAG: ldr p{{[01]}}, [sp, #6, mul vl]
|
||||
%local0 = alloca <vscale x 2 x i1>
|
||||
%local1 = alloca <vscale x 2 x i1>
|
||||
load volatile <vscale x 2 x i1>, <vscale x 2 x i1>* %local0
|
||||
load volatile <vscale x 2 x i1>, <vscale x 2 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
; Predicate spills
|
||||
|
||||
define void @spill_nxv16i1(<vscale x 16 x i1> %v0, <vscale x 16 x i1> %v1) {
|
||||
; CHECK-LABEL: spill_nxv16i1
|
||||
; CHECK-DAG: str p{{[01]}}, [sp, #8, mul vl]
|
||||
; CHECK-DAG: str p{{[01]}}, [sp]
|
||||
%local0 = alloca <vscale x 16 x i1>
|
||||
%local1 = alloca <vscale x 16 x i1>
|
||||
store volatile <vscale x 16 x i1> %v0, <vscale x 16 x i1>* %local0
|
||||
store volatile <vscale x 16 x i1> %v1, <vscale x 16 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @spill_nxv8i1(<vscale x 8 x i1> %v0, <vscale x 8 x i1> %v1) {
|
||||
; CHECK-LABEL: spill_nxv8i1
|
||||
; CHECK-DAG: str p{{[01]}}, [sp, #4, mul vl]
|
||||
; CHECK-DAG: str p{{[01]}}, [sp]
|
||||
%local0 = alloca <vscale x 8 x i1>
|
||||
%local1 = alloca <vscale x 8 x i1>
|
||||
store volatile <vscale x 8 x i1> %v0, <vscale x 8 x i1>* %local0
|
||||
store volatile <vscale x 8 x i1> %v1, <vscale x 8 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @spill_nxv4i1(<vscale x 4 x i1> %v0, <vscale x 4 x i1> %v1) {
|
||||
; CHECK-LABEL: spill_nxv4i1
|
||||
; CHECK-DAG: str p{{[01]}}, [sp, #6, mul vl]
|
||||
; CHECK-DAG: str p{{[01]}}, [sp, #4, mul vl]
|
||||
%local0 = alloca <vscale x 4 x i1>
|
||||
%local1 = alloca <vscale x 4 x i1>
|
||||
store volatile <vscale x 4 x i1> %v0, <vscale x 4 x i1>* %local0
|
||||
store volatile <vscale x 4 x i1> %v1, <vscale x 4 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @spill_nxv2i1(<vscale x 2 x i1> %v0, <vscale x 2 x i1> %v1) {
|
||||
; CHECK-LABEL: spill_nxv2i1
|
||||
; CHECK-DAG: str p{{[01]}}, [sp, #7, mul vl]
|
||||
; CHECK-DAG: str p{{[01]}}, [sp, #6, mul vl]
|
||||
%local0 = alloca <vscale x 2 x i1>
|
||||
%local1 = alloca <vscale x 2 x i1>
|
||||
store volatile <vscale x 2 x i1> %v0, <vscale x 2 x i1>* %local0
|
||||
store volatile <vscale x 2 x i1> %v1, <vscale x 2 x i1>* %local1
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user