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[WebAssembly] Codegen for v128.storeX_lane instructions
Replace the experimental clang builtins and LLVM intrinsics for these instructions with normal codegen patterns. Resolves PR50435. Differential Revision: https://reviews.llvm.org/D106019
This commit is contained in:
Thomas Lively
parent
daf8a095a1
commit
3c50e4a7a7
@ -186,32 +186,6 @@ def int_wasm_load64_zero :
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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// These intrinsics do not mark their lane index arguments as immediate because
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// that changes the corresponding SDNode from ISD::Constant to
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// ISD::TargetConstant, which would require extra complications in the ISel
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// tablegen patterns. TODO: Replace these intrinsic with normal ISel patterns
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// once the load_lane instructions are merged to the proposal.
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def int_wasm_store8_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i8_ty>, llvm_v16i8_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store16_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i16_ty>, llvm_v8i16_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store32_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i32_ty>, llvm_v4i32_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store64_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i64_ty>, llvm_v2i64_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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// TODO: Replace this intrinsic with normal ISel patterns once popcnt is merged
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// to the proposal.
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def int_wasm_popcnt :
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@ -767,35 +767,6 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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Info.align = Align(1);
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Info.flags = MachineMemOperand::MOLoad;
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return true;
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case Intrinsic::wasm_store8_lane:
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case Intrinsic::wasm_store16_lane:
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case Intrinsic::wasm_store32_lane:
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case Intrinsic::wasm_store64_lane: {
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MVT MemVT;
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switch (Intrinsic) {
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case Intrinsic::wasm_store8_lane:
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MemVT = MVT::i8;
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break;
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case Intrinsic::wasm_store16_lane:
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MemVT = MVT::i16;
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break;
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case Intrinsic::wasm_store32_lane:
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MemVT = MVT::i32;
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break;
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case Intrinsic::wasm_store64_lane:
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MemVT = MVT::i64;
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break;
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default:
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llvm_unreachable("unexpected intrinsic");
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}
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Info.opc = ISD::INTRINSIC_VOID;
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Info.memVT = MemVT;
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Info.ptrVal = I.getArgOperand(0);
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Info.offset = 0;
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Info.align = Align(1);
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Info.flags = MachineMemOperand::MOStore;
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return true;
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}
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default:
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return false;
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}
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@ -385,15 +385,13 @@ multiclass SIMDStoreLane<Vec vec, bits<32> simdop> {
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} // mayStore = 1, UseNamedOperandTable = 1
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}
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// TODO: Also support v4f32 and v2f64 once the instructions are merged
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// to the proposal
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defm "" : SIMDStoreLane<I8x16, 0x58>;
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defm "" : SIMDStoreLane<I16x8, 0x59>;
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defm "" : SIMDStoreLane<I32x4, 0x5a>;
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defm "" : SIMDStoreLane<I64x2, 0x5b>;
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// Select stores with no constant offset.
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multiclass StoreLanePatNoOffset<Vec vec, Intrinsic kind> {
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multiclass StoreLanePatNoOffset<Vec vec, SDPatternOperator kind> {
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def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
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(!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>,
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Requires<[HasAddr32]>;
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@ -402,13 +400,26 @@ multiclass StoreLanePatNoOffset<Vec vec, Intrinsic kind> {
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Requires<[HasAddr64]>;
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}
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defm : StoreLanePatNoOffset<I8x16, int_wasm_store8_lane>;
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defm : StoreLanePatNoOffset<I16x8, int_wasm_store16_lane>;
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defm : StoreLanePatNoOffset<I32x4, int_wasm_store32_lane>;
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defm : StoreLanePatNoOffset<I64x2, int_wasm_store64_lane>;
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def store8_lane :
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PatFrag<(ops node:$ptr, node:$vec, node:$idx),
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(truncstorei8 (i32 (vector_extract $vec, $idx)), $ptr)>;
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def store16_lane :
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PatFrag<(ops node:$ptr, node:$vec, node:$idx),
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(truncstorei16 (i32 (vector_extract $vec, $idx)), $ptr)>;
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def store32_lane :
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PatFrag<(ops node:$ptr, node:$vec, node:$idx),
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(store (i32 (vector_extract $vec, $idx)), $ptr)>;
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def store64_lane :
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PatFrag<(ops node:$ptr, node:$vec, node:$idx),
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(store (i64 (vector_extract $vec, $idx)), $ptr)>;
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// TODO: floating point lanes as well
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// TODO: Also support the other store patterns for store_lane once the
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// instructions are merged to the proposal.
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let AddedComplexity = 1 in {
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defm : StoreLanePatNoOffset<I8x16, store8_lane>;
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defm : StoreLanePatNoOffset<I16x8, store16_lane>;
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defm : StoreLanePatNoOffset<I32x4, store32_lane>;
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defm : StoreLanePatNoOffset<I64x2, store64_lane>;
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}
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//===----------------------------------------------------------------------===//
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// Constructing SIMD values
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@ -13,8 +13,7 @@ target triple = "wasm32-unknown-unknown"
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; t8: ch = store<(store 8 into `i64* undef`, align 1)> t3:1, t24, undef:i32, undef:i32
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; t9: ch = WebAssemblyISD::RETURN t8
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; CHECK: i64x2.extract_lane
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; CHECK-NEXT: i64.store
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; CHECK: v128.store64_lane
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define void @build_pair_i32s() {
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entry:
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%0 = load <4 x i32>, <4 x i32>* undef, align 16
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@ -8,11 +8,6 @@
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target triple = "wasm32-unknown-unknown"
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declare void @llvm.wasm.store8.lane(i8*, <16 x i8>, i32)
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declare void @llvm.wasm.store16.lane(i16*, <8 x i16>, i32)
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declare void @llvm.wasm.store32.lane(i32*, <4 x i32>, i32)
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declare void @llvm.wasm.store64.lane(i64*, <2 x i64>, i32)
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;===----------------------------------------------------------------------------
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; v128.load8_lane / v128.store8_lane
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;===----------------------------------------------------------------------------
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@ -150,7 +145,8 @@ define void @store_lane_i8_no_offset(<16 x i8> %v, i8* %p) {
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store8_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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tail call void @llvm.wasm.store8.lane(i8* %p, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* %p
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ret void
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}
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@ -167,7 +163,8 @@ define void @store_lane_i8_with_folded_offset(<16 x i8> %v, i8* %p) {
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%q = ptrtoint i8* %p to i32
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%r = add nuw i32 %q, 24
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%s = inttoptr i32 %r to i8*
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tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* %s
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ret void
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}
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@ -182,7 +179,8 @@ define void @store_lane_i8_with_folded_gep_offset(<16 x i8> %v, i8* %p) {
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; CHECK-NEXT: v128.store8_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = getelementptr inbounds i8, i8* %p, i32 6
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tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* %s
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ret void
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}
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@ -197,7 +195,8 @@ define void @store_lane_i8_with_unfolded_gep_negative_offset(<16 x i8> %v, i8* %
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; CHECK-NEXT: v128.store8_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = getelementptr inbounds i8, i8* %p, i32 -6
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tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* %s
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ret void
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}
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@ -214,7 +213,8 @@ define void @store_lane_i8_with_unfolded_offset(<16 x i8> %v, i8* %p) {
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%q = ptrtoint i8* %p to i32
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%r = add nsw i32 %q, 24
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%s = inttoptr i32 %r to i8*
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tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* %s
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ret void
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}
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@ -229,7 +229,8 @@ define void @store_lane_i8_with_unfolded_gep_offset(<16 x i8> %v, i8* %p) {
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; CHECK-NEXT: v128.store8_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = getelementptr i8, i8* %p, i32 6
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tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* %s
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ret void
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}
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@ -242,7 +243,8 @@ define void @store_lane_i8_to_numeric_address(<16 x i8> %v) {
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; CHECK-NEXT: v128.store8_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = inttoptr i32 42 to i8*
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tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* %s
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ret void
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}
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@ -254,7 +256,8 @@ define void @store_lane_i8_from_global_address(<16 x i8> %v) {
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store8_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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tail call void @llvm.wasm.store8.lane(i8* @gv_i8, <16 x i8> %v, i32 0)
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%x = extractelement <16 x i8> %v, i32 0
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store i8 %x, i8* @gv_i8
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ret void
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}
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@ -393,9 +396,10 @@ define void @store_lane_i16_no_offset(<8 x i16> %v, i16* %p) {
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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tail call void @llvm.wasm.store16.lane(i16* %p, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* %p
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ret void
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}
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@ -407,12 +411,13 @@ define void @store_lane_i16_with_folded_offset(<8 x i16> %v, i16* %p) {
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; CHECK-NEXT: i32.const 24
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; CHECK-NEXT: i32.add
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%q = ptrtoint i16* %p to i32
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%r = add nuw i32 %q, 24
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%s = inttoptr i32 %r to i16*
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tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* %s
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ret void
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}
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@ -424,10 +429,11 @@ define void @store_lane_i16_with_folded_gep_offset(<8 x i16> %v, i16* %p) {
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; CHECK-NEXT: i32.const 12
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; CHECK-NEXT: i32.add
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = getelementptr inbounds i16, i16* %p, i32 6
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tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* %s
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ret void
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}
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@ -439,10 +445,11 @@ define void @store_lane_i16_with_unfolded_gep_negative_offset(<8 x i16> %v, i16*
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; CHECK-NEXT: i32.const -12
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; CHECK-NEXT: i32.add
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = getelementptr inbounds i16, i16* %p, i32 -6
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tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* %s
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ret void
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}
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@ -454,12 +461,13 @@ define void @store_lane_i16_with_unfolded_offset(<8 x i16> %v, i16* %p) {
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; CHECK-NEXT: i32.const 24
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; CHECK-NEXT: i32.add
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%q = ptrtoint i16* %p to i32
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%r = add nsw i32 %q, 24
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%s = inttoptr i32 %r to i16*
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tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* %s
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ret void
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}
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@ -471,10 +479,11 @@ define void @store_lane_i16_with_unfolded_gep_offset(<8 x i16> %v, i16* %p) {
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; CHECK-NEXT: i32.const 12
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; CHECK-NEXT: i32.add
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = getelementptr i16, i16* %p, i32 6
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tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* %s
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ret void
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}
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@ -484,10 +493,11 @@ define void @store_lane_i16_to_numeric_address(<8 x i16> %v) {
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.const 42
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%s = inttoptr i32 42 to i16*
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tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* %s
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ret void
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}
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@ -497,9 +507,10 @@ define void @store_lane_i16_from_global_address(<8 x i16> %v) {
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i32.const gv_i16
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store16_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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tail call void @llvm.wasm.store16.lane(i16* @gv_i16, <8 x i16> %v, i32 0)
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%x = extractelement <8 x i16> %v, i32 0
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store i16 %x, i16* @gv_i16
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ret void
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}
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@ -638,9 +649,10 @@ define void @store_lane_i32_no_offset(<4 x i32> %v, i32* %p) {
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store32_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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tail call void @llvm.wasm.store32.lane(i32* %p, <4 x i32> %v, i32 0)
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%x = extractelement <4 x i32> %v, i32 0
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store i32 %x, i32* %p
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ret void
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}
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@ -652,12 +664,13 @@ define void @store_lane_i32_with_folded_offset(<4 x i32> %v, i32* %p) {
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; CHECK-NEXT: i32.const 24
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; CHECK-NEXT: i32.add
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
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; CHECK-NEXT: v128.store32_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%q = ptrtoint i32* %p to i32
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%r = add nuw i32 %q, 24
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%s = inttoptr i32 %r to i32*
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -669,10 +682,11 @@ define void @store_lane_i32_with_folded_gep_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i32, i32* %p, i32 6
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -684,10 +698,11 @@ define void @store_lane_i32_with_unfolded_gep_negative_offset(<4 x i32> %v, i32*
|
||||
; CHECK-NEXT: i32.const -24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i32, i32* %p, i32 -6
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -699,12 +714,13 @@ define void @store_lane_i32_with_unfolded_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i32* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i32*
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -716,10 +732,11 @@ define void @store_lane_i32_with_unfolded_gep_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i32, i32* %p, i32 6
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -729,10 +746,11 @@ define void @store_lane_i32_to_numeric_address(<4 x i32> %v) {
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i32*
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -742,9 +760,10 @@ define void @store_lane_i32_from_global_address(<4 x i32> %v) {
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i32
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store32.lane(i32* @gv_i32, <4 x i32> %v, i32 0)
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* @gv_i32
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -883,9 +902,10 @@ define void @store_lane_i64_no_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store64.lane(i64* %p, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -897,12 +917,13 @@ define void @store_lane_i64_with_folded_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i64* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i64*
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -914,10 +935,11 @@ define void @store_lane_i64_with_folded_gep_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-NEXT: i32.const 48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i64, i64* %p, i32 6
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -929,10 +951,11 @@ define void @store_lane_i64_with_unfolded_gep_negative_offset(<2 x i64> %v, i64*
|
||||
; CHECK-NEXT: i32.const -48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i64, i64* %p, i32 -6
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -944,12 +967,13 @@ define void @store_lane_i64_with_unfolded_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i64* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i64*
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -961,10 +985,11 @@ define void @store_lane_i64_with_unfolded_gep_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-NEXT: i32.const 48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i64, i64* %p, i32 6
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -974,10 +999,11 @@ define void @store_lane_i64_to_numeric_address(<2 x i64> %v) {
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i64*
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %s
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -987,8 +1013,9 @@ define void @store_lane_i64_from_global_address(<2 x i64> %v) {
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i64
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store64.lane(i64* @gv_i64, <2 x i64> %v, i32 0)
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* @gv_i64
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -161,6 +161,34 @@ define <16 x i8> @load_lane_i8_a2(i8* %p, <16 x i8> %v) {
|
||||
ret <16 x i8> %v1
|
||||
}
|
||||
|
||||
; 1 is the default alignment for v128.store8_lane so no attribute is needed.
|
||||
define void @store_lane_i8_a1(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_a1:
|
||||
; CHECK: .functype store_lane_i8_a1 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <16 x i8> %v, i32 0
|
||||
store i8 %x, i8* %p, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; 2 is greater than the default alignment so it is ignored.
|
||||
define void @store_lane_i8_a2(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_a2:
|
||||
; CHECK: .functype store_lane_i8_a2 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <16 x i8> %v, i32 0
|
||||
store i8 %x, i8* %p, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 8 x i16
|
||||
; ==============================================================================
|
||||
@ -462,6 +490,47 @@ define <8 x i16> @load_lane_i16_a4(i16* %p, <8 x i16> %v) {
|
||||
ret <8 x i16> %v1
|
||||
}
|
||||
|
||||
define void @store_lane_i16_a1(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_a1:
|
||||
; CHECK: .functype store_lane_i16_a1 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <8 x i16> %v, i32 0
|
||||
store i16 %x, i16* %p, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; 2 is the default alignment for v128.store16_lane so no attribute is needed.
|
||||
define void @store_lane_i16_a2(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_a2:
|
||||
; CHECK: .functype store_lane_i16_a2 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <8 x i16> %v, i32 0
|
||||
store i16 %x, i16* %p, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; 4 is greater than the default alignment so it is ignored.
|
||||
define void @store_lane_i16_a4(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_a4:
|
||||
; CHECK: .functype store_lane_i16_a4 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <8 x i16> %v, i32 0
|
||||
store i16 %x, i16* %p, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 4 x i32
|
||||
; ==============================================================================
|
||||
@ -789,6 +858,60 @@ define <4 x i32> @load_lane_i32_a8(i32* %p, <4 x i32> %v) {
|
||||
ret <4 x i32> %v1
|
||||
}
|
||||
|
||||
define void @store_lane_i32_a1(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_a1:
|
||||
; CHECK: .functype store_lane_i32_a1 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %p, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_a2(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_a2:
|
||||
; CHECK: .functype store_lane_i32_a2 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0:p2align=1, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %p, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; 4 is the default alignment for v128.store32_lane so no attribute is needed.
|
||||
define void @store_lane_i32_a4(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_a4:
|
||||
; CHECK: .functype store_lane_i32_a4 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %p, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; 8 is greater than the default alignment so it is ignored.
|
||||
define void @store_lane_i32_a8(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_a8:
|
||||
; CHECK: .functype store_lane_i32_a8 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <4 x i32> %v, i32 0
|
||||
store i32 %x, i32* %p, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 2 x i64
|
||||
; ==============================================================================
|
||||
@ -1023,6 +1146,73 @@ define <2 x i64> @load_lane_i64_a16(i64* %p, <2 x i64> %v) {
|
||||
ret <2 x i64> %v1
|
||||
}
|
||||
|
||||
define void @store_lane_i64_a1(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_a1:
|
||||
; CHECK: .functype store_lane_i64_a1 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %p, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_a2(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_a2:
|
||||
; CHECK: .functype store_lane_i64_a2 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=1, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %p, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_a4(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_a4:
|
||||
; CHECK: .functype store_lane_i64_a4 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0:p2align=2, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %p, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; 8 is the default alignment for v128.store64_lane so no attribute is needed.
|
||||
define void @store_lane_i64_a8(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_a8:
|
||||
; CHECK: .functype store_lane_i64_a8 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %p, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; 16 is greater than the default alignment so it is ignored.
|
||||
define void @store_lane_i64_a16(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_a16:
|
||||
; CHECK: .functype store_lane_i64_a16 (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%x = extractelement <2 x i64> %v, i32 0
|
||||
store i64 %x, i64* %p, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 4 x float
|
||||
; ==============================================================================
|
||||
|
||||
Loading…
Reference in New Issue
Block a user