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[InstCombine] Recommit: Shift amount reassociation: shl-trunc-shl pattern
This was initially committed in r368059 but got reverted in r368084 because there was a faulty logic in how the shift amounts type mismatch was being handled (it simply wasn't). I've added an explicit bailout before we SimplifyAddInst() - i don't think it's designed in general to handle differently-typed values, even though the actual problem only comes from ConstantExpr's. I have also changed the common type deduction, to not just blindly look past zext, but try to do that so that in the end types match. Differential Revision: https://reviews.llvm.org/D65380 llvm-svn: 368141
This commit is contained in:
Roman Lebedev
parent
d4d1331456
commit
3c5960b14a
@ -1270,6 +1270,12 @@ inline CastClass_match<OpTy, Instruction::ZExt> m_ZExt(const OpTy &Op) {
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return CastClass_match<OpTy, Instruction::ZExt>(Op);
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}
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template <typename OpTy>
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inline match_combine_or<CastClass_match<OpTy, Instruction::ZExt>, OpTy>
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m_ZExtOrSelf(const OpTy &Op) {
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return m_CombineOr(m_ZExt(Op), Op);
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}
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template <typename OpTy>
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inline match_combine_or<CastClass_match<OpTy, Instruction::ZExt>,
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CastClass_match<OpTy, Instruction::SExt>>
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@ -27,42 +27,90 @@ using namespace PatternMatch;
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// This is valid for any shift, but they must be identical.
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static Instruction *
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reassociateShiftAmtsOfTwoSameDirectionShifts(BinaryOperator *Sh0,
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const SimplifyQuery &SQ) {
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// Look for: (x shiftopcode ShAmt0) shiftopcode ShAmt1
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Value *X, *ShAmt1, *ShAmt0;
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const SimplifyQuery &SQ,
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InstCombiner::BuilderTy &Builder) {
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// Look for a shift of some instruction, ignore zext of shift amount if any.
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Instruction *Sh0Op0;
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Value *ShAmt0;
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if (!match(Sh0,
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m_Shift(m_Instruction(Sh0Op0), m_ZExtOrSelf(m_Value(ShAmt0)))))
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return nullptr;
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// If there is a truncation between the two shifts, we must make note of it
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// and look through it. The truncation imposes additional constraints on the
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// transform.
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Instruction *Sh1;
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if (!match(Sh0, m_Shift(m_CombineAnd(m_Shift(m_Value(X), m_Value(ShAmt1)),
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m_Instruction(Sh1)),
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m_Value(ShAmt0))))
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Value *Trunc = nullptr;
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match(Sh0Op0,
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m_CombineOr(m_CombineAnd(m_Trunc(m_Instruction(Sh1)), m_Value(Trunc)),
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m_Instruction(Sh1)));
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// Inner shift: (x shiftopcode ShAmt1)
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// Like with other shift, ignore zext of shift amount if any.
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Value *X, *ShAmt1;
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if (!match(Sh1, m_Shift(m_Value(X), m_ZExtOrSelf(m_Value(ShAmt1)))))
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return nullptr;
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// We have two shift amounts from two different shifts. The types of those
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// shift amounts may not match. If that's the case let's bailout now..
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if (ShAmt0->getType() != ShAmt1->getType())
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return nullptr;
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// The shift opcodes must be identical.
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Instruction::BinaryOps ShiftOpcode = Sh0->getOpcode();
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if (ShiftOpcode != Sh1->getOpcode())
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return nullptr;
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// Did we match a pattern with truncation ?
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if (Trunc) {
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// For right-shifts we can't do any such simplifications. Leave as-is.
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if (ShiftOpcode != Instruction::BinaryOps::Shl)
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return nullptr; // FIXME: still could perform constant-folding.
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// If we saw truncation, we'll need to produce extra instruction,
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// and for that one of the operands of the shift must be one-use.
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if (!match(Sh0, m_c_BinOp(m_OneUse(m_Value()), m_Value())))
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return nullptr;
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}
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// Can we fold (ShAmt0+ShAmt1) ?
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Value *NewShAmt = SimplifyBinOp(Instruction::BinaryOps::Add, ShAmt0, ShAmt1,
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SQ.getWithInstruction(Sh0));
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auto *NewShAmt = dyn_cast_or_null<Constant>(
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SimplifyAddInst(ShAmt0, ShAmt1, /*isNSW=*/false, /*isNUW=*/false,
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SQ.getWithInstruction(Sh0)));
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if (!NewShAmt)
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return nullptr; // Did not simplify.
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// Is the new shift amount smaller than the bit width?
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// FIXME: could also rely on ConstantRange.
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unsigned BitWidth = X->getType()->getScalarSizeInBits();
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if (!match(NewShAmt, m_SpecificInt_ICMP(ICmpInst::Predicate::ICMP_ULT,
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APInt(BitWidth, BitWidth))))
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return nullptr;
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// Is the new shift amount smaller than the bit width of inner shift?
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if (!match(NewShAmt, m_SpecificInt_ICMP(
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ICmpInst::Predicate::ICMP_ULT,
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APInt(NewShAmt->getType()->getScalarSizeInBits(),
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X->getType()->getScalarSizeInBits()))))
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return nullptr; // FIXME: could perform constant-folding.
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// All good, we can do this fold.
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NewShAmt = ConstantExpr::getZExtOrBitCast(NewShAmt, X->getType());
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BinaryOperator *NewShift = BinaryOperator::Create(ShiftOpcode, X, NewShAmt);
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// If both of the original shifts had the same flag set, preserve the flag.
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if (ShiftOpcode == Instruction::BinaryOps::Shl) {
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NewShift->setHasNoUnsignedWrap(Sh0->hasNoUnsignedWrap() &&
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Sh1->hasNoUnsignedWrap());
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NewShift->setHasNoSignedWrap(Sh0->hasNoSignedWrap() &&
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Sh1->hasNoSignedWrap());
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} else {
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NewShift->setIsExact(Sh0->isExact() && Sh1->isExact());
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// The flags can only be propagated if there wasn't a trunc.
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if (!Trunc) {
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// If the pattern did not involve trunc, and both of the original shifts
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// had the same flag set, preserve the flag.
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if (ShiftOpcode == Instruction::BinaryOps::Shl) {
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NewShift->setHasNoUnsignedWrap(Sh0->hasNoUnsignedWrap() &&
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Sh1->hasNoUnsignedWrap());
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NewShift->setHasNoSignedWrap(Sh0->hasNoSignedWrap() &&
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Sh1->hasNoSignedWrap());
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} else {
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NewShift->setIsExact(Sh0->isExact() && Sh1->isExact());
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}
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}
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return NewShift;
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Instruction *Ret = NewShift;
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if (Trunc) {
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Builder.Insert(NewShift);
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Ret = CastInst::Create(Instruction::Trunc, NewShift, Sh0->getType());
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}
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return Ret;
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}
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// If we have some pattern that leaves only some low bits set, and then performs
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@ -158,7 +206,7 @@ Instruction *InstCombiner::commonShiftTransforms(BinaryOperator &I) {
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return Res;
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if (Instruction *NewShift =
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reassociateShiftAmtsOfTwoSameDirectionShifts(&I, SQ))
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reassociateShiftAmtsOfTwoSameDirectionShifts(&I, SQ, Builder))
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return NewShift;
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// (C1 shift (A add C2)) -> (C1 shift C2) shift A)
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@ -12,12 +12,8 @@
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define i16 @t0(i32 %x, i16 %y) {
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; CHECK-LABEL: @t0(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -24
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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@ -31,12 +27,8 @@ define i16 @t0(i32 %x, i16 %y) {
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define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[T0:%.*]] = sub <2 x i16> <i16 32, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <2 x i16> [[T0]] to <2 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <2 x i32> [[T2]] to <2 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <2 x i16> [[Y]], <i16 -24, i16 -24>
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; CHECK-NEXT: [[T5:%.*]] = shl <2 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 8>
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; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T5]]
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;
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%t0 = sub <2 x i16> <i16 32, i16 32>, %y
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@ -50,12 +42,8 @@ define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
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define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
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; CHECK-LABEL: @t2_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = sub <2 x i16> <i16 32, i16 30>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <2 x i16> [[T0]] to <2 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <2 x i32> [[T2]] to <2 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <2 x i16> [[Y]], <i16 -24, i16 0>
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; CHECK-NEXT: [[T5:%.*]] = shl <2 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 30>
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; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T5]]
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;
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%t0 = sub <2 x i16> <i16 32, i16 30>, %y
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@ -71,12 +59,8 @@ define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
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define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t3_vec_nonsplat_undef0(
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; CHECK-NEXT: [[T0:%.*]] = sub <3 x i16> <i16 32, i16 undef, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -24, i16 -24, i16 -24>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
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; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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@ -90,12 +74,8 @@ define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
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define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t4_vec_nonsplat_undef1(
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; CHECK-NEXT: [[T0:%.*]] = sub <3 x i16> <i16 32, i16 32, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -24, i16 undef, i16 -24>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
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; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
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@ -109,12 +89,8 @@ define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t5_vec_nonsplat_undef1(
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; CHECK-NEXT: [[T0:%.*]] = sub <3 x i16> <i16 32, i16 undef, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -24, i16 undef, i16 -24>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
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; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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@ -137,9 +113,9 @@ define i16 @t6_extrause0(i32 %x, i16 %y) {
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -24
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; CHECK-NEXT: call void @use16(i16 [[T3]])
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X]] to i16
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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@ -154,13 +130,10 @@ define i16 @t6_extrause0(i32 %x, i16 %y) {
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define i16 @t7_extrause1(i32 %x, i16 %y) {
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; CHECK-LABEL: @t7_extrause1(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -24
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -24
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; CHECK-NEXT: call void @use16(i16 [[T4]])
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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@ -252,3 +225,20 @@ define i16 @n11(i32 %x, i16 %y) {
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%t5 = shl i16 %t3, %t4
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ret i16 %t3
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}
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; Bit width mismatch of shit amount
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@Y32 = global i32 42
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@Y16 = global i16 42
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define i16 @t01(i32 %x) {
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; CHECK-LABEL: @t01(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], ptrtoint (i32* @Y32 to i32)
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; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[T0]] to i16
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; CHECK-NEXT: [[T2:%.*]] = shl i16 [[T1]], ptrtoint (i16* @Y16 to i16)
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; CHECK-NEXT: ret i16 [[T2]]
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;
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%t0 = shl i32 %x, ptrtoint (i32* @Y32 to i32)
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%t1 = trunc i32 %t0 to i16
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%t2 = shl i16 %t1, ptrtoint (i16* @Y16 to i16)
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ret i16 %t2
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}
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