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[X86][SSE] Add support for combining target shuffles to binary BLEND

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We already had support for 1-input BLEND with zero - this adds support for 2-input BLEND as well.

llvm-svn: 283040
This commit is contained in:
Simon Pilgrim 2016-10-01 16:04:28 +00:00
parent 2b25d6a062
commit 3c7330116c
3 changed files with 34 additions and 12 deletions
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34
lib/Target/X86/X86ISelLowering.cpp
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@ -25160,7 +25160,7 @@ static bool matchBinaryPermuteVectorShuffle(MVT MaskVT, ArrayRef<int> Mask,
}
}
// Attempt to blend with zero.
// Attempt to combine to X86ISD::BLENDI.
if (NumMaskElts <= 8 && ((Subtarget.hasSSE41() && MaskVT.is128BitVector()) ||
(Subtarget.hasAVX() && MaskVT.is256BitVector()))) {
// Determine a type compatible with X86ISD::BLENDI.
@ -25180,12 +25180,13 @@ static bool matchBinaryPermuteVectorShuffle(MVT MaskVT, ArrayRef<int> Mask,
BlendVT = MVT::v8f32;
}
unsigned BlendSize = BlendVT.getVectorNumElements();
unsigned MaskRatio = BlendSize / NumMaskElts;
// Can we blend with zero?
if (isSequentialOrUndefOrZeroInRange(Mask, /*Pos*/ 0, /*Size*/ NumMaskElts,
/*Low*/ 0) &&
NumMaskElts <= BlendVT.getVectorNumElements()) {
unsigned BlendSize = BlendVT.getVectorNumElements();
unsigned MaskRatio = BlendSize / NumMaskElts;
PermuteImm = 0;
for (unsigned i = 0; i != BlendSize; ++i)
if (Mask[i / MaskRatio] < 0)
@ -25196,6 +25197,31 @@ static bool matchBinaryPermuteVectorShuffle(MVT MaskVT, ArrayRef<int> Mask,
ShuffleVT = BlendVT;
return true;
}
// Attempt to match as a binary blend.
if (NumMaskElts <= BlendVT.getVectorNumElements()) {
bool MatchBlend = true;
for (int i = 0; i != NumMaskElts; ++i) {
int M = Mask[i];
if (M == SM_SentinelUndef)
continue;
else if (M == SM_SentinelZero)
MatchBlend = false;
else if ((M != i) && (M != (i + NumMaskElts)))
MatchBlend = false;
}
if (MatchBlend) {
PermuteImm = 0;
for (unsigned i = 0; i != BlendSize; ++i)
if ((int)NumMaskElts <= Mask[i / MaskRatio])
PermuteImm |= 1u << i;
Shuffle = X86ISD::BLENDI;
ShuffleVT = BlendVT;
return true;
}
}
}
// Attempt to combine to INSERTPS.

6
test/CodeGen/X86/vector-shuffle-256-v16.ll
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@ -851,13 +851,11 @@ define <16 x i16> @shuffle_v16i16_16_16_16_16_04_05_06_07_24_24_24_24_12_13_14_1
; AVX1-LABEL: shuffle_v16i16_16_16_16_16_04_05_06_07_24_24_24_24_12_13_14_15:
; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;

6
test/CodeGen/X86/vector-shuffle-256-v32.ll
View File

@ -1157,15 +1157,13 @@ define <32 x i8> @shuffle_v32i8_32_32_32_32_32_32_32_32_08_09_10_11_12_13_14_15_
; AVX1-LABEL: shuffle_v32i8_32_32_32_32_32_32_32_32_08_09_10_11_12_13_14_15_48_48_48_48_48_48_48_48_24_25_26_27_28_29_30_31:
; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;