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[X86][SSE] Don't duplicate Lower256IntArith functionality in LowerMul. NFC.

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LowerMul v32i8 on AVX2 needs to split the 256-bit sources to allow sign-extension back to v16i16 to occur. Since this is basically the same as Lower256IntArith we simplify by using that here instead.

llvm-svn: 264506
This commit is contained in:
Simon Pilgrim 2016-03-26 09:29:04 +00:00
parent d5b67d75ce
commit 3c89786d54
1 changed files with 5 additions and 13 deletions
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18
lib/Target/X86/X86ISelLowering.cpp
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@ -18905,22 +18905,14 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget,
SDValue A = Op.getOperand(0);
SDValue B = Op.getOperand(1);
// Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
// Lower v16i8/v32i8 mul as sign-extension to v8i16/v16i16 vector
// pairs, multiply and truncate.
if (VT == MVT::v16i8 || VT == MVT::v32i8) {
if (Subtarget.hasInt256()) {
if (VT == MVT::v32i8) {
MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
SDValue Lo = DAG.getIntPtrConstant(0, dl);
SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
}
// For 256-bit vectors, split into 128-bit vectors to allow the
// sign-extension to occur.
if (VT == MVT::v32i8)
return Lower256IntArith(Op, DAG);
MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
return DAG.getNode(