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[llvm-mca] Improve code comments in LSUnit.{h, cpp}. NFC
llvm-svn: 342877
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@ -41,31 +41,31 @@ struct InstrDesc;
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/// This class optimistically assumes that loads don't alias store operations.
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/// Under this assumption, younger loads are always allowed to pass older
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/// stores (this would only affects rule 4).
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/// Essentially, this LSUnit doesn't attempt to run any sort alias analysis to
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/// predict when loads and stores don't alias with eachother.
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/// Essentially, this class doesn't perform any sort alias analysis to
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/// identify aliasing loads and stores.
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///
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/// To enforce aliasing between loads and stores, flag `AssumeNoAlias` must be
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/// set to `false` by the constructor of LSUnit.
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///
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/// In the case of write-combining memory, rule 2. could be relaxed to allow
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/// reordering of non-aliasing store operations. At the moment, this is not
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/// allowed.
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/// To put it in another way, there is no option to specify a different memory
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/// type for memory operations (example: write-through, write-combining, etc.).
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/// Also, there is no way to weaken the memory model, and this unit currently
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/// doesn't support write-combining behavior.
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/// Note that this class doesn't know about the existence of different memory
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/// types for memory operations (example: write-through, write-combining, etc.).
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/// Derived classes are responsible for implementing that extra knowledge, and
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/// provide different sets of rules for loads and stores by overriding method
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/// `isReady()`.
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/// To emulate a write-combining memory type, rule 2. must be relaxed in a
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/// derived class to enable the reordering of non-aliasing store operations.
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///
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/// No assumptions are made on the size of the store buffer.
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/// As mentioned before, this class doesn't perform alias analysis.
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/// Consequently, LSUnit doesn't know how to identify cases where
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/// store-to-load forwarding may occur.
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/// No assumptions are made by this class on the size of the store buffer. This
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/// class doesn't know how to identify cases where store-to-load forwarding may
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/// occur.
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///
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/// LSUnit doesn't attempt to predict whether a load or store hits or misses
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/// the L1 cache. To be more specific, LSUnit doesn't know anything about
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/// the cache hierarchy and memory types.
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/// cache hierarchy and memory types.
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/// It only knows if an instruction "mayLoad" and/or "mayStore". For loads, the
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/// scheduling model provides an "optimistic" load-to-use latency (which usually
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/// matches the load-to-use latency for when there is a hit in the L1D).
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/// Derived classes may expand this knowledge.
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///
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/// Class MCInstrDesc in LLVM doesn't know about serializing operations, nor
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/// memory-barrier like instructions.
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@ -89,25 +89,32 @@ bool LSUnit::isReady(const InstRef &IR) const {
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if (IsALoad && !LoadBarriers.empty()) {
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unsigned LoadBarrierIndex = *LoadBarriers.begin();
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// A younger load cannot pass a older load barrier.
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if (Index > LoadBarrierIndex)
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return false;
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// A load barrier cannot pass a older load.
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if (Index == LoadBarrierIndex && Index != *LoadQueue.begin())
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return false;
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}
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if (IsAStore && !StoreBarriers.empty()) {
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unsigned StoreBarrierIndex = *StoreBarriers.begin();
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// A younger store cannot pass a older store barrier.
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if (Index > StoreBarrierIndex)
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return false;
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// A store barrier cannot pass a older store.
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if (Index == StoreBarrierIndex && Index != *StoreQueue.begin())
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return false;
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}
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// A load may not pass a previous store unless flag 'NoAlias' is set.
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// A load may pass a previous load.
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if (NoAlias && IsALoad)
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return true;
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if (StoreQueue.size()) {
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// Check if this memory operation is younger than the older store.
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// A load may not pass a previous store.
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// A store may not pass a previous store.
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if (Index > *StoreQueue.begin())
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return false;
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}
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@ -123,6 +130,9 @@ bool LSUnit::isReady(const InstRef &IR) const {
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return true;
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// There is at least one younger load.
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//
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// A store may not pass a previous load.
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// A load may pass a previous load.
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return !IsAStore;
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}
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