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R600/SI: Remove SI_BUFFER_RSRC pseudo

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Just use REG_SEQUENCE directly, so there are fewer
instructions to need to deal with later.

llvm-svn: 220056
This commit is contained in:
Matt Arsenault 2014-10-17 17:42:56 +00:00
parent 99ffd17333
commit 3ce8aba254
4 changed files with 24 additions and 43 deletions
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29
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
View File

@ -944,21 +944,38 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset);
}
static SDValue buildSMovImm32(SelectionDAG *DAG, SDLoc DL, uint64_t Val) {
SDValue K = DAG->getTargetConstant(Val, MVT::i32);
return SDValue(DAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
}
static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr,
uint32_t RsrcDword1, uint64_t RsrcDword2And3) {
SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
if (RsrcDword1)
if (RsrcDword1) {
PtrHi = SDValue(DAG->getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
DAG->getConstant(RsrcDword1, MVT::i32)), 0);
}
SDValue DataLo = DAG->getTargetConstant(
RsrcDword2And3 & APInt::getAllOnesValue(32).getZExtValue(), MVT::i32);
SDValue DataHi = DAG->getTargetConstant(RsrcDword2And3 >> 32, MVT::i32);
SDValue DataLo = buildSMovImm32(DAG, DL,
RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
const SDValue Ops[] = { PtrLo, PtrHi, DataLo, DataHi };
return SDValue(DAG->getMachineNode(AMDGPU::SI_BUFFER_RSRC, DL,
const SDValue Ops[] = {
DAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
PtrLo,
DAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
PtrHi,
DAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
DataLo,
DAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
DataHi,
DAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
};
return SDValue(DAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
MVT::v4i32, Ops), 0);
}

30
lib/Target/R600/SIISelLowering.cpp
View File

@ -623,36 +623,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
case AMDGPU::SI_BUFFER_RSRC: {
unsigned SuperReg = MI->getOperand(0).getReg();
unsigned Args[4];
for (unsigned i = 0, e = 4; i < e; ++i) {
MachineOperand &Arg = MI->getOperand(i + 1);
if (Arg.isReg()) {
Args[i] = Arg.getReg();
continue;
}
assert(Arg.isImm());
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), Reg)
.addImm(Arg.getImm());
Args[i] = Reg;
}
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE),
SuperReg)
.addReg(Args[0])
.addImm(AMDGPU::sub0)
.addReg(Args[1])
.addImm(AMDGPU::sub1)
.addReg(Args[2])
.addImm(AMDGPU::sub2)
.addReg(Args[3])
.addImm(AMDGPU::sub3);
MI->eraseFromParent();
break;
}
case AMDGPU::V_SUB_F64: {
unsigned DestReg = MI->getOperand(0).getReg();
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)

6
lib/Target/R600/SIInstructions.td
View File

@ -1794,12 +1794,6 @@ def SI_ADDR64_RSRC : InstSI <
"", []
>;
def SI_BUFFER_RSRC : InstSI <
(outs SReg_128:$srsrc),
(ins SReg_32:$ptr_lo, SReg_32:$ptr_hi, SSrc_32:$data_lo, SSrc_32:$data_hi),
"", []
>;
def V_SUB_F64 : InstSI <
(outs VReg_64:$dst),
(ins VReg_64:$src0, VReg_64:$src1),

2
test/CodeGen/R600/smrd.ll
View File

@ -37,8 +37,8 @@ entry:
; SMRD load with a 64-bit offset
; CHECK-LABEL: {{^}}smrd3:
; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0
; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4
; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0 ;
; FIXME: We don't need to copy these values to VGPRs
; CHECK-DAG: V_MOV_B32_e32 v[[VLO:[0-9]+]], s[[SLO]]
; CHECK-DAG: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[SHI]]