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[AArch64] v8.3-a complex number support
New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. Differential Revision: https://reviews.llvm.org/D36792 llvm-svn: 312228
This commit is contained in:
Sam Parker
parent
42bd8958bb
commit
3d30332768
@ -9391,6 +9391,238 @@ multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
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}
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} // let Predicates = [HasNeon, HasRDM]
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//----------------------------------------------------------------------------
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// ARMv8.3 Complex ADD/MLA instructions
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//----------------------------------------------------------------------------
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class ComplexRotationOperand<int Angle, int Remainder, string Type>
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: AsmOperandClass {
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let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">";
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let DiagnosticType = "InvalidComplexRotation" # Type;
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let Name = "ComplexRotation" # Type;
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}
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def complexrotateop : Operand<i32> {
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let ParserMatchClass = ComplexRotationOperand<90, 0, "Even">;
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let PrintMethod = "printComplexRotationOp<90, 0>";
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}
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def complexrotateopodd : Operand<i32> {
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let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd">;
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let PrintMethod = "printComplexRotationOp<180, 90>";
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}
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode,
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RegisterOperand regtype, Operand rottype,
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string asm, string kind, list<dag> pattern>
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: I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
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"{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
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"|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "", pattern>,
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Sched<[WriteV]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<5> Rm;
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bits<1> rot;
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let Inst{31} = 0;
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let Inst{30} = Q;
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let Inst{29} = U;
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let Inst{28-24} = 0b01110;
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let Inst{23-22} = size;
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let Inst{21} = 0;
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let Inst{20-16} = Rm;
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let Inst{15-13} = opcode;
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// Non-tied version (FCADD) only has one rotation bit
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let Inst{12} = rot;
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let Inst{11} = 0;
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let Inst{10} = 1;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Rd;
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}
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multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype,
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string asm, SDPatternOperator OpNode>{
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let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
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def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype,
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asm, ".4h",
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[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
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(v4f16 V64:$Rn),
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(v4f16 V64:$Rm),
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(rottype i32:$rot)))]>;
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def v8f16 : BaseSIMDThreeSameVectorComplex<1, U, 0b01, opcode, V128, rottype,
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asm, ".8h",
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[(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
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(v8f16 V128:$Rn),
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(v8f16 V128:$Rm),
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(rottype i32:$rot)))]>;
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}
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let Predicates = [HasV8_3a, HasNEON] in {
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def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype,
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asm, ".2s",
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[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
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(v2f32 V64:$Rn),
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(v2f32 V64:$Rm),
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(rottype i32:$rot)))]>;
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def v4f32 : BaseSIMDThreeSameVectorComplex<1, U, 0b10, opcode, V128, rottype,
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asm, ".4s",
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[(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
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(v4f32 V128:$Rn),
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(v4f32 V128:$Rm),
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(rottype i32:$rot)))]>;
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def v2f64 : BaseSIMDThreeSameVectorComplex<1, U, 0b11, opcode, V128, rottype,
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asm, ".2d",
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[(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
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(v2f64 V128:$Rn),
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(v2f64 V128:$Rm),
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(rottype i32:$rot)))]>;
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}
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}
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size,
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bits<3> opcode,
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RegisterOperand regtype,
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Operand rottype, string asm,
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string kind, list<dag> pattern>
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: I<(outs regtype:$dst),
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(ins regtype:$Rd, regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
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"{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
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"|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "$Rd = $dst", pattern>,
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Sched<[WriteV]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<5> Rm;
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bits<2> rot;
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let Inst{31} = 0;
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let Inst{30} = Q;
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let Inst{29} = U;
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let Inst{28-24} = 0b01110;
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let Inst{23-22} = size;
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let Inst{21} = 0;
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let Inst{20-16} = Rm;
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let Inst{15-13} = opcode;
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let Inst{12-11} = rot;
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let Inst{10} = 1;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Rd;
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}
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multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode,
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Operand rottype, string asm,
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SDPatternOperator OpNode> {
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let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
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def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64,
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rottype, asm, ".4h",
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[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
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(v4f16 V64:$Rn),
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(v4f16 V64:$Rm),
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(rottype i32:$rot)))]>;
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def v8f16 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b01, opcode, V128,
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rottype, asm, ".8h",
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[(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
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(v8f16 V128:$Rn),
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(v8f16 V128:$Rm),
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(rottype i32:$rot)))]>;
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}
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let Predicates = [HasV8_3a, HasNEON] in {
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def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64,
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rottype, asm, ".2s",
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[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
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(v2f32 V64:$Rn),
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(v2f32 V64:$Rm),
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(rottype i32:$rot)))]>;
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def v4f32 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b10, opcode, V128,
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rottype, asm, ".4s",
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[(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
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(v4f32 V128:$Rn),
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(v4f32 V128:$Rm),
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(rottype i32:$rot)))]>;
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def v2f64 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b11, opcode, V128,
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rottype, asm, ".2d",
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[(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
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(v2f64 V128:$Rn),
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(v2f64 V128:$Rm),
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(rottype i32:$rot)))]>;
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}
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}
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size,
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bit opc1, bit opc2, RegisterOperand dst_reg,
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RegisterOperand lhs_reg,
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RegisterOperand rhs_reg, Operand vec_idx,
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Operand rottype, string asm, string apple_kind,
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string dst_kind, string lhs_kind,
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string rhs_kind, list<dag> pattern>
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: I<(outs dst_reg:$dst),
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(ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx, rottype:$rot),
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asm,
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"{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind #
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"$idx, $rot" # "|" # apple_kind #
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"\t$Rd, $Rn, $Rm$idx, $rot}", "$Rd = $dst", pattern>,
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Sched<[WriteV]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<5> Rm;
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bits<2> rot;
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let Inst{31} = 0;
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let Inst{30} = Q;
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let Inst{29} = U;
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let Inst{28} = Scalar;
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let Inst{27-24} = 0b1111;
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let Inst{23-22} = size;
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// Bit 21 must be set by the derived class.
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let Inst{20-16} = Rm;
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let Inst{15} = opc1;
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let Inst{14-13} = rot;
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let Inst{12} = opc2;
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// Bit 11 must be set by the derived class.
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let Inst{10} = 0;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Rd;
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}
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// The complex instructions index by pairs of elements, so the VectorIndexes
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// don't match the lane types, and the index bits are different to the other
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// classes.
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multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
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string asm, SDPatternOperator OpNode> {
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let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in {
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def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
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V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h",
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".4h", ".h", []> {
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bits<1> idx;
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let Inst{11} = 0;
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let Inst{21} = idx{0};
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}
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def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
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V128, V128, V128, VectorIndexS, rottype, asm, ".8h",
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".8h", ".8h", ".h", []> {
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bits<2> idx;
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let Inst{11} = idx{1};
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let Inst{21} = idx{0};
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}
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} // Predicates = [HasV8_3a,HasNEON,HasFullFP16]
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let Predicates = [HasV8_3a,HasNEON] in {
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def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
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V128, V128, V128, VectorIndexD, rottype, asm, ".4s",
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".4s", ".4s", ".s", []> {
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bits<1> idx;
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let Inst{11} = idx{0};
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let Inst{21} = 0;
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}
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} // Predicates = [HasV8_3a,HasNEON]
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}
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//----------------------------------------------------------------------------
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// Crypto extensions
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//----------------------------------------------------------------------------
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@ -460,6 +460,15 @@ let Predicates = [HasRCPC] in {
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def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;
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}
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// v8.3a complex add and multiply-accumulate. No predicate here, that is done
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// inside the multiclass as the FP16 versions need different predicates.
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defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop,
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"fcmla", null_frag>;
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defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd,
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"fcadd", null_frag>;
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defm FCMLA : SIMDIndexedTiedComplexHSD<1, 0, 1, complexrotateop, "fcmla",
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null_frag>;
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let Predicates = [HasV8_3a] in {
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// v8.3a Pointer Authentication
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let Uses = [LR], Defs = [LR] in {
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@ -835,6 +835,17 @@ public:
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AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum);
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}
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template<int64_t Angle, int64_t Remainder>
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bool isComplexRotation() const {
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if (!isImm()) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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uint64_t Value = CE->getValue();
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return (Value % Angle == Remainder && Value <= 270);
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}
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/// Is this a vector list with the type implicit (presumably attached to the
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/// instruction itself)?
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template <unsigned NumRegs> bool isImplicitlyTypedVectorList() const {
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@ -1527,6 +1538,18 @@ public:
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Inst.addOperand(MCOperand::createImm((~Value >> Shift) & 0xffff));
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}
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void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
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Inst.addOperand(MCOperand::createImm(MCE->getValue() / 90));
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}
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void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
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Inst.addOperand(MCOperand::createImm((MCE->getValue() - 90) / 180));
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}
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void print(raw_ostream &OS) const override;
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static std::unique_ptr<AArch64Operand>
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@ -3402,6 +3425,10 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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return Error(Loc, "expected readable system register");
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case Match_MSR:
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return Error(Loc, "expected writable system register or pstate");
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case Match_InvalidComplexRotationEven:
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return Error(Loc, "complex rotation must be 0, 90, 180 or 270.");
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case Match_InvalidComplexRotationOdd:
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return Error(Loc, "complex rotation must be 90 or 270.");
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case Match_MnemonicFail: {
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std::string Suggestion = AArch64MnemonicSpellCheck(
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((AArch64Operand &)*Operands[0]).getToken(),
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@ -3802,6 +3829,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidIndexS:
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case Match_InvalidIndexD:
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case Match_InvalidLabel:
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case Match_InvalidComplexRotationEven:
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case Match_InvalidComplexRotationOdd:
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case Match_MSR:
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case Match_MRS: {
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if (ErrorInfo >= Operands.size())
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@ -1331,3 +1331,12 @@ void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
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uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
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O << format("#%#016llx", Val);
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}
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template<int64_t Angle, int64_t Remainder>
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void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned Val = MI->getOperand(OpNo).getImm();
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O << "#" << (Val * Angle) + Remainder;
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}
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@ -158,6 +158,9 @@ protected:
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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template<int64_t Angle, int64_t Remainder>
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void printComplexRotationOp(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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template<unsigned size>
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void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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148
test/MC/AArch64/armv8.3a-complex.s
Normal file
148
test/MC/AArch64/armv8.3a-complex.s
Normal file
@ -0,0 +1,148 @@
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16
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// RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-NO-FP16 %s < %t
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
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// RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-FP16 %s < %t
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A
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// ==== FCMLA vector ====
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// Types
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fcmla v0.4h, v1.4h, v2.4h, #0
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// FP16: fcmla v0.4h, v1.4h, v2.4h, #0 // encoding: [0x20,0xc4,0x42,0x2e]
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// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
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// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
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fcmla v0.8h, v1.8h, v2.8h, #0
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// FP16: fcmla v0.8h, v1.8h, v2.8h, #0 // encoding: [0x20,0xc4,0x42,0x6e]
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// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
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// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
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fcmla v0.2s, v1.2s, v2.2s, #0
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// CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]
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// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
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fcmla v0.4s, v1.4s, v2.4s, #0
|
||||
// CHECK: fcmla v0.4s, v1.4s, v2.4s, #0 // encoding: [0x20,0xc4,0x82,0x6e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.2d, v1.2d, v2.2d, #0
|
||||
// CHECK: fcmla v0.2d, v1.2d, v2.2d, #0 // encoding: [0x20,0xc4,0xc2,0x6e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
|
||||
// Rotations
|
||||
fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.2s, v1.2s, v2.2s, #90
|
||||
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xcc,0x82,0x2e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.2s, v1.2s, v2.2s, #180
|
||||
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #180 // encoding: [0x20,0xd4,0x82,0x2e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.2s, v1.2s, v2.2s, #270
|
||||
// CHECK: fcmla v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xdc,0x82,0x2e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
|
||||
// Invalid rotations
|
||||
fcmla v0.2s, v1.2s, v2.2s, #1
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
|
||||
fcmla v0.2s, v1.2s, v2.2s, #360
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
|
||||
fcmla v0.2s, v1.2s, v2.2s, #-90
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
|
||||
|
||||
// ==== FCADD vector ====
|
||||
// Types
|
||||
fcadd v0.4h, v1.4h, v2.4h, #90
|
||||
// FP16: fcadd v0.4h, v1.4h, v2.4h, #90 // encoding: [0x20,0xe4,0x42,0x2e]
|
||||
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
|
||||
// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcadd v0.8h, v1.8h, v2.8h, #90
|
||||
// FP16: fcadd v0.8h, v1.8h, v2.8h, #90 // encoding: [0x20,0xe4,0x42,0x6e]
|
||||
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
|
||||
// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcadd v0.4s, v1.4s, v2.4s, #90
|
||||
// CHECK: fcadd v0.4s, v1.4s, v2.4s, #90 // encoding: [0x20,0xe4,0x82,0x6e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcadd v0.2d, v1.2d, v2.2d, #90
|
||||
// CHECK: fcadd v0.2d, v1.2d, v2.2d, #90 // encoding: [0x20,0xe4,0xc2,0x6e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
|
||||
// Rotations
|
||||
fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcadd v0.2s, v1.2s, v2.2s, #270
|
||||
// CHECK: fcadd v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xf4,0x82,0x2e]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
|
||||
// Invalid rotations
|
||||
fcadd v0.2s, v1.2s, v2.2s, #1
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
|
||||
fcadd v0.2s, v1.2s, v2.2s, #360
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
|
||||
fcadd v0.2s, v1.2s, v2.2s, #-90
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
|
||||
fcadd v0.2s, v1.2s, v2.2s, #0
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
|
||||
fcadd v0.2s, v1.2s, v2.2s, #180
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270.
|
||||
|
||||
// ==== FCMLA indexed ====
|
||||
// Types
|
||||
fcmla v0.4h, v1.4h, v2.h[0], #0
|
||||
// FP16: fcmla v0.4h, v1.4h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x2f]
|
||||
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
|
||||
// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.8h, v1.8h, v2.h[0], #0
|
||||
// FP16: fcmla v0.8h, v1.8h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x6f]
|
||||
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
|
||||
// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.2s, v1.2s, v2.s[0], #0
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction
|
||||
fcmla v0.4s, v1.4s, v2.s[0], #0
|
||||
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #0 // encoding: [0x20,0x10,0x82,0x6f]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.2d, v1.2d, v2.d[0], #0
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction
|
||||
|
||||
// Rotations
|
||||
fcmla v0.4s, v1.4s, v2.s[0], #90
|
||||
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #90 // encoding: [0x20,0x30,0x82,0x6f]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.4s, v1.4s, v2.s[0], #180
|
||||
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #180 // encoding: [0x20,0x50,0x82,0x6f]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.4s, v1.4s, v2.s[0], #270
|
||||
// CHECK: fcmla v0.4s, v1.4s, v2.s[0], #270 // encoding: [0x20,0x70,0x82,0x6f]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
|
||||
// Valid indices
|
||||
fcmla v0.4h, v1.4h, v2.h[1], #0
|
||||
// FP16: fcmla v0.4h, v1.4h, v2.h[1], #0 // encoding: [0x20,0x10,0x62,0x2f]
|
||||
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
|
||||
// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.8h, v1.8h, v2.h[3], #0
|
||||
// FP16: fcmla v0.8h, v1.8h, v2.h[3], #0 // encoding: [0x20,0x18,0x62,0x6f]
|
||||
// STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16
|
||||
// NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
fcmla v0.4s, v1.4s, v2.s[1], #0
|
||||
// CHECK: fcmla v0.4s, v1.4s, v2.s[1], #0 // encoding: [0x20,0x18,0x82,0x6f]
|
||||
// NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a
|
||||
|
||||
// Invalid indices
|
||||
fcmla v0.4h, v1.4h, v2.h[2], #0
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
|
||||
fcmla v0.8h, v1.8h, v2.h[4], #0
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3].
|
||||
fcmla v0.4s, v1.4s, v2.s[2], #0
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
|
||||
|
||||
// Invalid rotations
|
||||
fcmla v0.4s, v1.4s, v2.s[0], #1
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
|
||||
fcmla v0.4s, v1.4s, v2.s[0], #360
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
|
||||
fcmla v0.4s, v1.4s, v2.s[0], #-90
|
||||
// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270.
|
||||
101
test/MC/Disassembler/AArch64/armv8.3a-complex.txt
Normal file
101
test/MC/Disassembler/AArch64/armv8.3a-complex.txt
Normal file
@ -0,0 +1,101 @@
|
||||
# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK
|
||||
# RUN: FileCheck %s < %t --check-prefix=NO-FP16
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,+fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
|
||||
# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.3a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A
|
||||
|
||||
###### FCMLA vector
|
||||
[0x20,0xc4,0x42,0x2e]
|
||||
# FP16: fcmla v0.4h, v1.4h, v2.4h, #0
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xc4,0x42,0x6e]
|
||||
# FP16: fcmla v0.8h, v1.8h, v2.8h, #0
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xc4,0x82,0x2e]
|
||||
# CHECK: fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xc4,0x82,0x6e]
|
||||
# CHECK: fcmla v0.4s, v1.4s, v2.4s, #0
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xc4,0xc2,0x6e]
|
||||
# CHECK: fcmla v0.2d, v1.2d, v2.2d, #0
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
|
||||
|
||||
[0x20,0xc4,0x82,0x2e]
|
||||
# CHECK: fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xcc,0x82,0x2e]
|
||||
# CHECK: fcmla v0.2s, v1.2s, v2.2s, #90
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xd4,0x82,0x2e]
|
||||
# CHECK: fcmla v0.2s, v1.2s, v2.2s, #180
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xdc,0x82,0x2e]
|
||||
# CHECK: fcmla v0.2s, v1.2s, v2.2s, #270
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
|
||||
|
||||
###### FCADD vector
|
||||
[0x20,0xe4,0x42,0x2e]
|
||||
# FP16: fcadd v0.4h, v1.4h, v2.4h, #90
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xe4,0x42,0x6e]
|
||||
# FP16: fcadd v0.8h, v1.8h, v2.8h, #90
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xe4,0x82,0x2e]
|
||||
# CHECK: fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xe4,0x82,0x6e]
|
||||
# CHECK: fcadd v0.4s, v1.4s, v2.4s, #90
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xe4,0xc2,0x6e]
|
||||
# CHECK: fcadd v0.2d, v1.2d, v2.2d, #90
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
|
||||
|
||||
[0x20,0xe4,0x82,0x2e]
|
||||
# CHECK: fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0xf4,0x82,0x2e]
|
||||
# CHECK: fcadd v0.2s, v1.2s, v2.2s, #270
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
|
||||
[0x20,0x10,0x42,0x2f]
|
||||
# FP16: fcmla v0.4h, v1.4h, v2.h[0], #0
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0x10,0x42,0x6f]
|
||||
# FP16: fcmla v0.8h, v1.8h, v2.h[0], #0
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0x10,0x82,0x6f]
|
||||
# CHECK: fcmla v0.4s, v1.4s, v2.s[0], #0
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
|
||||
|
||||
[0x20,0x30,0x82,0x6f]
|
||||
# CHECK: fcmla v0.4s, v1.4s, v2.s[0], #90
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0x50,0x82,0x6f]
|
||||
# CHECK: fcmla v0.4s, v1.4s, v2.s[0], #180
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0x70,0x82,0x6f]
|
||||
# CHECK: fcmla v0.4s, v1.4s, v2.s[0], #270
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
|
||||
|
||||
[0x20,0x10,0x62,0x2f]
|
||||
# FP16: fcmla v0.4h, v1.4h, v2.h[1], #0
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0x18,0x62,0x6f]
|
||||
# FP16: fcmla v0.8h, v1.8h, v2.h[3], #0
|
||||
# NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
# NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
[0x20,0x18,0x82,0x6f]
|
||||
# CHECK: fcmla v0.4s, v1.4s, v2.s[1], #0
|
||||
# NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
|
||||
Loading…
Reference in New Issue
Block a user