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Teach the codegen about instructions used for SSE spill code, allowing it
to optimize cases where it has to spill a lot llvm-svn: 27801
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7821901005
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@ -56,6 +56,8 @@ unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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case X86::FpLD64m:
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case X86::FpLD64m:
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case X86::MOVSSrm:
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case X86::MOVSSrm:
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case X86::MOVSDrm:
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case X86::MOVSDrm:
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case X86::MOVAPSrm:
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case X86::MOVAPDrm:
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if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
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if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
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MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 1 &&
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MI->getOperand(2).getImmedValue() == 1 &&
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@ -79,6 +81,8 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
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case X86::FpSTP64m:
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case X86::FpSTP64m:
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case X86::MOVSSmr:
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case X86::MOVSSmr:
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case X86::MOVSDmr:
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case X86::MOVSDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDmr:
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if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
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if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
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MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
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MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
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MI->getOperand(1).getImmedValue() == 1 &&
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MI->getOperand(1).getImmedValue() == 1 &&
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