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[X86] Regenerate fmin/fmax reduction tests
Add missing check-prefixes + v1f32 tests
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@ -1,15 +1,23 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512
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;
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; vXf32
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;
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define float @test_v1f32(<1 x float> %a0) {
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; ALL-LABEL: test_v1f32:
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; ALL: # %bb.0:
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; ALL-NEXT: retq
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%1 = call nnan float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a0)
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ret float %1
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}
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define float @test_v2f32(<2 x float> %a0) {
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; SSE2-LABEL: test_v2f32:
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; SSE2: # %bb.0:
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@ -458,10 +466,10 @@ define half @test_v2f16(<2 x half> %a0) nounwind {
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; SSE-NEXT: subq $16, %rsp
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; SSE-NEXT: movl %edi, %ebx
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; SSE-NEXT: movzwl %si, %edi
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; SSE-NEXT: callq __gnu_h2f_ieee
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; SSE-NEXT: callq __gnu_h2f_ieee@PLT
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; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
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; SSE-NEXT: movzwl %bx, %edi
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; SSE-NEXT: callq __gnu_h2f_ieee
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; SSE-NEXT: callq __gnu_h2f_ieee@PLT
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: cmpunordss %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm2
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@ -471,7 +479,7 @@ define half @test_v2f16(<2 x half> %a0) nounwind {
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; SSE-NEXT: andnps %xmm3, %xmm1
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; SSE-NEXT: orps %xmm2, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: callq __gnu_f2h_ieee
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; SSE-NEXT: callq __gnu_f2h_ieee@PLT
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; SSE-NEXT: addq $16, %rsp
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; SSE-NEXT: popq %rbx
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; SSE-NEXT: retq
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@ -482,16 +490,16 @@ define half @test_v2f16(<2 x half> %a0) nounwind {
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; AVX-NEXT: subq $16, %rsp
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; AVX-NEXT: movl %esi, %ebx
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; AVX-NEXT: movzwl %di, %edi
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; AVX-NEXT: callq __gnu_h2f_ieee
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; AVX-NEXT: callq __gnu_h2f_ieee@PLT
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; AVX-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; AVX-NEXT: movzwl %bx, %edi
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; AVX-NEXT: callq __gnu_h2f_ieee
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; AVX-NEXT: callq __gnu_h2f_ieee@PLT
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; AVX-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Reload
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; AVX-NEXT: # xmm2 = mem[0],zero,zero,zero
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; AVX-NEXT: vmaxss %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vcmpunordss %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: callq __gnu_f2h_ieee
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; AVX-NEXT: callq __gnu_f2h_ieee@PLT
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; AVX-NEXT: addq $16, %rsp
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; AVX-NEXT: popq %rbx
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; AVX-NEXT: retq
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@ -514,6 +522,7 @@ define half @test_v2f16(<2 x half> %a0) nounwind {
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%1 = call nnan half @llvm.vector.reduce.fmax.v2f16(<2 x half> %a0)
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ret half %1
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}
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declare float @llvm.vector.reduce.fmax.v1f32(<1 x float>)
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declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
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declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
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declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)
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@ -1,10 +1,10 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512VL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512,AVX512BW
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VL
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;
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; vXf32
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@ -1,10 +1,10 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512
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;
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; vXf32
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@ -465,10 +465,10 @@ define half @test_v2f16(<2 x half> %a0) nounwind {
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; SSE-NEXT: subq $16, %rsp
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; SSE-NEXT: movl %edi, %ebx
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; SSE-NEXT: movzwl %si, %edi
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; SSE-NEXT: callq __gnu_h2f_ieee
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; SSE-NEXT: callq __gnu_h2f_ieee@PLT
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; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
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; SSE-NEXT: movzwl %bx, %edi
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; SSE-NEXT: callq __gnu_h2f_ieee
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; SSE-NEXT: callq __gnu_h2f_ieee@PLT
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: cmpunordss %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm2
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@ -478,7 +478,7 @@ define half @test_v2f16(<2 x half> %a0) nounwind {
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; SSE-NEXT: andnps %xmm3, %xmm1
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; SSE-NEXT: orps %xmm2, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: callq __gnu_f2h_ieee
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; SSE-NEXT: callq __gnu_f2h_ieee@PLT
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; SSE-NEXT: addq $16, %rsp
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; SSE-NEXT: popq %rbx
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; SSE-NEXT: retq
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@ -489,16 +489,16 @@ define half @test_v2f16(<2 x half> %a0) nounwind {
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; AVX-NEXT: subq $16, %rsp
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; AVX-NEXT: movl %esi, %ebx
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; AVX-NEXT: movzwl %di, %edi
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; AVX-NEXT: callq __gnu_h2f_ieee
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; AVX-NEXT: callq __gnu_h2f_ieee@PLT
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; AVX-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; AVX-NEXT: movzwl %bx, %edi
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; AVX-NEXT: callq __gnu_h2f_ieee
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; AVX-NEXT: callq __gnu_h2f_ieee@PLT
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; AVX-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Reload
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; AVX-NEXT: # xmm2 = mem[0],zero,zero,zero
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; AVX-NEXT: vminss %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vcmpunordss %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: callq __gnu_f2h_ieee
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; AVX-NEXT: callq __gnu_f2h_ieee@PLT
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; AVX-NEXT: addq $16, %rsp
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; AVX-NEXT: popq %rbx
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; AVX-NEXT: retq
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@ -1,15 +1,23 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512VL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512,AVX512BW
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VL
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;
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; vXf32
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;
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define float @test_v1f32(<1 x float> %a0) {
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; ALL-LABEL: test_v1f32:
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; ALL: # %bb.0:
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; ALL-NEXT: retq
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%1 = call float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a0)
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ret float %1
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}
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define float @test_v2f32(<2 x float> %a0) {
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; SSE2-LABEL: test_v2f32:
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; SSE2: # %bb.0:
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@ -1086,6 +1094,7 @@ define double @test_v16f64(<16 x double> %a0) {
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ret double %1
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}
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declare float @llvm.vector.reduce.fmin.v1f32(<1 x float>)
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declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
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declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
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declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
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