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AArch64: Mark vector long multiplication as expand.

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There are no patterns for this. This was already fixed for ARM64 but I forgot
to apply it to AArch64 too.

llvm-svn: 207515
This commit is contained in:
Benjamin Kramer 2014-04-29 09:37:54 +00:00
parent 6630aee422
commit 3e3e43e656
2 changed files with 19 additions and 0 deletions
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5
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -514,6 +514,11 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
> VT1.getVectorElementType().getSizeInBits())
setTruncStoreAction(VT, VT1, Expand);
}
setOperationAction(ISD::MULHS, VT, Expand);
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
setOperationAction(ISD::MULHU, VT, Expand);
setOperationAction(ISD::UMUL_LOHI, VT, Expand);
}
// There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.

14
test/CodeGen/AArch64/neon-idiv.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
; RUN: llc -mtriple=arm64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
define <4 x i32> @test1(<4 x i32> %a) {
%rem = srem <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %rem
; CHECK-LABEL: test1
; FIXME: Can we lower this more efficiently?
; CHECK: mul
; CHECK: mul
; CHECK: mul
; CHECK: mul
}