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[SystemZ] Avoid scalarization of [SU]INT_TO_FP ISD-nodes.
The type legalizer will scalarize vector conversions from integer to floating point if the source element size is less than that of the result. This is avoided now by inserting a zero/sign-extension of the source vector before type legalization. Review: Ulrich Weigand Differential revision: https://reviews.llvm.org/D75978
This commit is contained in:
Jonas Paulsson
parent
84d5d3fdf6
commit
3e697060c0
@ -641,6 +641,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::FP_ROUND);
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setTargetDAGCombine(ISD::STRICT_FP_ROUND);
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setTargetDAGCombine(ISD::FP_EXTEND);
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setTargetDAGCombine(ISD::SINT_TO_FP);
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setTargetDAGCombine(ISD::UINT_TO_FP);
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setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
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setTargetDAGCombine(ISD::BSWAP);
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setTargetDAGCombine(ISD::SDIV);
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@ -6081,6 +6083,32 @@ SDValue SystemZTargetLowering::combineFP_EXTEND(
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return SDValue();
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}
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SDValue SystemZTargetLowering::combineINT_TO_FP(
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SDNode *N, DAGCombinerInfo &DCI) const {
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if (DCI.Level != BeforeLegalizeTypes)
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return SDValue();
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unsigned Opcode = N->getOpcode();
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EVT OutVT = N->getValueType(0);
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SelectionDAG &DAG = DCI.DAG;
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SDValue Op = N->getOperand(0);
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unsigned OutScalarBits = OutVT.getScalarSizeInBits();
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unsigned InScalarBits = Op->getValueType(0).getScalarSizeInBits();
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// Insert an extension before type-legalization to avoid scalarization, e.g.:
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// v2f64 = uint_to_fp v2i16
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// =>
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// v2f64 = uint_to_fp (v2i64 zero_extend v2i16)
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if (OutVT.isVector() && OutScalarBits > InScalarBits) {
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MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(OutVT.getScalarSizeInBits()),
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OutVT.getVectorNumElements());
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unsigned ExtOpcode =
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(Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND);
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SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op);
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return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp);
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}
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return SDValue();
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}
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SDValue SystemZTargetLowering::combineBSWAP(
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SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -6408,6 +6436,8 @@ SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::FP_ROUND: return combineFP_ROUND(N, DCI);
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case ISD::STRICT_FP_EXTEND:
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case ISD::FP_EXTEND: return combineFP_EXTEND(N, DCI);
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: return combineINT_TO_FP(N, DCI);
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case ISD::BSWAP: return combineBSWAP(N, DCI);
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case SystemZISD::BR_CCMASK: return combineBR_CCMASK(N, DCI);
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case SystemZISD::SELECT_CCMASK: return combineSELECT_CCMASK(N, DCI);
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@ -642,6 +642,7 @@ private:
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SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
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131
test/CodeGen/SystemZ/vec-move-23.ll
Normal file
131
test/CodeGen/SystemZ/vec-move-23.ll
Normal file
@ -0,0 +1,131 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefixes=CHECK,Z14
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s -check-prefixes=CHECK,Z15
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;
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; Check that int-to-fp conversions from a narrower type get a vector extension.
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define void @fun0(<2 x i8> %Src, <2 x double>* %Dst) {
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; CHECK-LABEL: fun0:
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; CHECK: vuphb %v0, %v24
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; CHECK-NEXT: vuphh %v0, %v0
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; CHECK-NEXT: vuphf %v0, %v0
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; CHECK-NEXT: vcdgb %v0, %v0, 0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%c = sitofp <2 x i8> %Src to <2 x double>
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store <2 x double> %c, <2 x double>* %Dst
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ret void
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}
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define void @fun1(<2 x i16> %Src, <2 x double>* %Dst) {
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; CHECK-LABEL: fun1:
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; CHECK: vuphh %v0, %v24
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; CHECK-NEXT: vuphf %v0, %v0
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; CHECK-NEXT: vcdgb %v0, %v0, 0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%c = sitofp <2 x i16> %Src to <2 x double>
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store <2 x double> %c, <2 x double>* %Dst
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ret void
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}
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define void @fun2(<2 x i32> %Src, <2 x double>* %Dst) {
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; CHECK-LABEL: fun2:
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; CHECK: vuphf %v0, %v24
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; CHECK-NEXT: vcdgb %v0, %v0, 0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%c = sitofp <2 x i32> %Src to <2 x double>
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store <2 x double> %c, <2 x double>* %Dst
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ret void
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}
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define void @fun3(<4 x i16> %Src, <4 x float>* %Dst) {
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; CHECK-LABEL: fun3:
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; Z14: vuphh %v0, %v24
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; Z14-NEXT: vlgvf %r0, %v0, 3
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; Z14-NEXT: cefbr %f1, %r0
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; Z14-NEXT: vlgvf %r0, %v0, 2
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; Z14-NEXT: cefbr %f2, %r0
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; Z14-NEXT: vlgvf %r0, %v0, 1
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; Z14-NEXT: vmrhf %v1, %v2, %v1
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; Z14-NEXT: cefbr %f2, %r0
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; Z14-NEXT: vlgvf %r0, %v0, 0
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; Z14-NEXT: cefbr %f0, %r0
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; Z14-NEXT: vmrhf %v0, %v0, %v2
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; Z14-NEXT: vmrhg %v0, %v0, %v1
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; Z14-NEXT: vst %v0, 0(%r2), 3
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; Z14-NEXT: br %r14
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; Z15: vuphh %v0, %v24
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; Z15-NEXT: vcefb %v0, %v0, 0, 0
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; Z15-NEXT: vst %v0, 0(%r2), 3
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; Z15-NEXT: br %r14
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%c = sitofp <4 x i16> %Src to <4 x float>
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store <4 x float> %c, <4 x float>* %Dst
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ret void
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}
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define void @fun4(<2 x i8> %Src, <2 x double>* %Dst) {
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; CHECK-LABEL: fun4:
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; CHECK: vuplhb %v0, %v24
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; CHECK-NEXT: vuplhh %v0, %v0
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; CHECK-NEXT: vuplhf %v0, %v0
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; CHECK-NEXT: vcdlgb %v0, %v0, 0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%c = uitofp <2 x i8> %Src to <2 x double>
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store <2 x double> %c, <2 x double>* %Dst
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ret void
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}
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define void @fun5(<2 x i16> %Src, <2 x double>* %Dst) {
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; CHECK-LABEL: fun5:
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; CHECK: vuplhh %v0, %v24
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; CHECK-NEXT: vuplhf %v0, %v0
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; CHECK-NEXT: vcdlgb %v0, %v0, 0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%c = uitofp <2 x i16> %Src to <2 x double>
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store <2 x double> %c, <2 x double>* %Dst
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ret void
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}
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define void @fun6(<2 x i32> %Src, <2 x double>* %Dst) {
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; CHECK-LABEL: fun6:
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; CHECK: vuplhf %v0, %v24
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; CHECK-NEXT: vcdlgb %v0, %v0, 0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%c = uitofp <2 x i32> %Src to <2 x double>
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store <2 x double> %c, <2 x double>* %Dst
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ret void
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}
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define void @fun7(<4 x i16> %Src, <4 x float>* %Dst) {
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; CHECK-LABEL: fun7:
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; Z14: vuplhh %v0, %v24
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; Z14-NEXT: vlgvf %r0, %v0, 3
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; Z14-NEXT: celfbr %f1, 0, %r0, 0
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; Z14-NEXT: vlgvf %r0, %v0, 2
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; Z14-NEXT: celfbr %f2, 0, %r0, 0
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; Z14-NEXT: vlgvf %r0, %v0, 1
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; Z14-NEXT: vmrhf %v1, %v2, %v1
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; Z14-NEXT: celfbr %f2, 0, %r0, 0
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; Z14-NEXT: vlgvf %r0, %v0, 0
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; Z14-NEXT: celfbr %f0, 0, %r0, 0
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; Z14-NEXT: vmrhf %v0, %v0, %v2
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; Z14-NEXT: vmrhg %v0, %v0, %v1
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; Z14-NEXT: vst %v0, 0(%r2), 3
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; Z14-NEXT: br %r14
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; Z15: vuplhh %v0, %v24
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; Z15-NEXT: vcelfb %v0, %v0, 0, 0
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; Z15-NEXT: vst %v0, 0(%r2), 3
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; Z15-NEXT: br %r14
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%c = uitofp <4 x i16> %Src to <4 x float>
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store <4 x float> %c, <4 x float>* %Dst
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ret void
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}
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