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Strength-reduce SmallVectors to arrays. NFCI.
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@ -133,7 +133,7 @@ const DILocation *DILocation::getMergedLocation(const DILocation *LocA,
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}
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Optional<unsigned> DILocation::encodeDiscriminator(unsigned BD, unsigned DF, unsigned CI) {
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SmallVector<unsigned, 3> Components = {BD, DF, CI};
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std::array<unsigned, 3> Components = {BD, DF, CI};
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uint64_t RemainingWork = 0U;
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// We use RemainingWork to figure out if we have no remaining components to
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// encode. For example: if BD != 0 but DF == 0 && CI == 0, we don't need to
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@ -15710,8 +15710,8 @@ SDValue AArch64TargetLowering::LowerFixedLengthVectorSetccToSVE(
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auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
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EVT CmpVT = Pg.getValueType();
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SmallVector<SDValue, 4> CmpOps = {Pg, Op1, Op2, Op.getOperand(2)};
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auto Cmp = DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT, CmpOps);
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auto Cmp = DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT,
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{Pg, Op1, Op2, Op.getOperand(2)});
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EVT PromoteVT = ContainerVT.changeTypeToInteger();
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auto Promote = DAG.getBoolExtOrTrunc(Cmp, DL, PromoteVT, InVT);
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@ -3156,7 +3156,7 @@ static bool mergeConditionalStoreToAddress(BasicBlock *PTB, BasicBlock *PFB,
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return true;
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};
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const SmallVector<StoreInst *, 2> FreeStores = {PStore, QStore};
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const std::array<StoreInst *, 2> FreeStores = {PStore, QStore};
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if (!MergeCondStoresAggressively &&
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(!IsWorthwhile(PTB, FreeStores) || !IsWorthwhile(PFB, FreeStores) ||
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!IsWorthwhile(QTB, FreeStores) || !IsWorthwhile(QFB, FreeStores)))
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