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[Hexagon] Add support for Hexagon/HVX v67 ISA
This commit is contained in:
Krzysztof Parzyszek
parent
93fa18dd41
commit
3ee90cb1f8
@ -573,15 +573,16 @@ enum {
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// Hexagon-specific e_flags
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enum {
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// Object processor version flags, bits[11:0]
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EF_HEXAGON_MACH_V2 = 0x00000001, // Hexagon V2
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EF_HEXAGON_MACH_V3 = 0x00000002, // Hexagon V3
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EF_HEXAGON_MACH_V4 = 0x00000003, // Hexagon V4
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EF_HEXAGON_MACH_V5 = 0x00000004, // Hexagon V5
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EF_HEXAGON_MACH_V55 = 0x00000005, // Hexagon V55
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EF_HEXAGON_MACH_V60 = 0x00000060, // Hexagon V60
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EF_HEXAGON_MACH_V62 = 0x00000062, // Hexagon V62
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EF_HEXAGON_MACH_V65 = 0x00000065, // Hexagon V65
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EF_HEXAGON_MACH_V66 = 0x00000066, // Hexagon V66
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EF_HEXAGON_MACH_V2 = 0x00000001, // Hexagon V2
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EF_HEXAGON_MACH_V3 = 0x00000002, // Hexagon V3
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EF_HEXAGON_MACH_V4 = 0x00000003, // Hexagon V4
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EF_HEXAGON_MACH_V5 = 0x00000004, // Hexagon V5
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EF_HEXAGON_MACH_V55 = 0x00000005, // Hexagon V55
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EF_HEXAGON_MACH_V60 = 0x00000060, // Hexagon V60
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EF_HEXAGON_MACH_V62 = 0x00000062, // Hexagon V62
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EF_HEXAGON_MACH_V65 = 0x00000065, // Hexagon V65
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EF_HEXAGON_MACH_V66 = 0x00000066, // Hexagon V66
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EF_HEXAGON_MACH_V67 = 0x00000067, // Hexagon V67
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// Highest ISA version flags
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EF_HEXAGON_ISA_MACH = 0x00000000, // Same as specified in bits[11:0]
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@ -595,6 +596,7 @@ enum {
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EF_HEXAGON_ISA_V62 = 0x00000062, // Hexagon V62 ISA
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EF_HEXAGON_ISA_V65 = 0x00000065, // Hexagon V65 ISA
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EF_HEXAGON_ISA_V66 = 0x00000066, // Hexagon V66 ISA
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EF_HEXAGON_ISA_V67 = 0x00000067, // Hexagon V67 ISA
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};
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// Hexagon-specific section indexes for common small data
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@ -3690,6 +3690,92 @@ Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>;
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def int_hexagon_S2_mask :
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Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg<0>, ImmArg<1>]>;
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// V67 Scalar Instructions.
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def int_hexagon_M7_dcmpyrw :
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Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">;
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def int_hexagon_M7_dcmpyrw_acc :
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Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">;
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def int_hexagon_M7_dcmpyrwc :
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Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">;
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def int_hexagon_M7_dcmpyrwc_acc :
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Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">;
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def int_hexagon_M7_dcmpyiw :
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Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">;
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def int_hexagon_M7_dcmpyiw_acc :
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Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">;
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def int_hexagon_M7_dcmpyiwc :
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Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">;
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def int_hexagon_M7_dcmpyiwc_acc :
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Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">;
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def int_hexagon_M7_vdmpy :
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Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">;
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def int_hexagon_M7_vdmpy_acc :
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Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">;
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def int_hexagon_M7_wcmpyrw :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">;
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def int_hexagon_M7_wcmpyrwc :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">;
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def int_hexagon_M7_wcmpyiw :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">;
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def int_hexagon_M7_wcmpyiwc :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">;
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def int_hexagon_M7_wcmpyrw_rnd :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">;
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def int_hexagon_M7_wcmpyrwc_rnd :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">;
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def int_hexagon_M7_wcmpyiw_rnd :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">;
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def int_hexagon_M7_wcmpyiwc_rnd :
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Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">;
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def int_hexagon_A7_croundd_ri :
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Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg<1>]>;
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def int_hexagon_A7_croundd_rr :
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Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_rr">;
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def int_hexagon_A7_clip :
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Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg<1>]>;
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def int_hexagon_A7_vclip :
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Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_vclip", [IntrNoMem, ImmArg<1>]>;
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def int_hexagon_F2_dfmax :
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Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmax", [IntrNoMem, Throws]>;
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def int_hexagon_F2_dfmin :
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Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmin", [IntrNoMem, Throws]>;
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def int_hexagon_F2_dfmpyfix :
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Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyfix", [IntrNoMem, Throws]>;
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def int_hexagon_F2_dfmpyll :
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Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>;
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def int_hexagon_F2_dfmpylh :
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Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpylh", [IntrNoMem, Throws]>;
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def int_hexagon_F2_dfmpyhh :
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Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>;
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// V60 HVX Instructions.
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def int_hexagon_V6_vS32b_qpred_ai :
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@ -350,6 +350,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
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BCase(EF_HEXAGON_MACH_V62);
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BCase(EF_HEXAGON_MACH_V65);
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BCase(EF_HEXAGON_MACH_V66);
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BCase(EF_HEXAGON_MACH_V67);
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BCase(EF_HEXAGON_ISA_V2);
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BCase(EF_HEXAGON_ISA_V3);
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BCase(EF_HEXAGON_ISA_V4);
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@ -359,6 +360,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
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BCase(EF_HEXAGON_ISA_V62);
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BCase(EF_HEXAGON_ISA_V65);
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BCase(EF_HEXAGON_ISA_V66);
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BCase(EF_HEXAGON_ISA_V67);
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break;
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case ELF::EM_AVR:
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BCase(EF_AVR_ARCH_AVR1);
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@ -312,6 +312,8 @@ public:
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bool iss30_2Imm() const { return true; }
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bool iss29_3Imm() const { return true; }
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bool iss27_2Imm() const { return CheckImmRange(27, 2, true, true, false); }
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bool iss10_0Imm() const { return CheckImmRange(10, 0, true, false, false); }
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bool iss10_6Imm() const { return CheckImmRange(10, 6, true, false, false); }
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bool iss9_0Imm() const { return CheckImmRange(9, 0, true, false, false); }
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bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); }
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bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); }
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@ -578,6 +580,7 @@ bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
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case Match_MnemonicFail:
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return Error(IDLoc, "unrecognized instruction");
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case Match_InvalidOperand:
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LLVM_FALLTHROUGH;
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case Match_InvalidTiedOperand:
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SMLoc ErrorLoc = IDLoc;
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if (ErrorInfo != ~0U) {
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@ -42,12 +42,19 @@ def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
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[ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
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ExtensionZReg]>;
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def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V67", "Hexagon HVX instructions",
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[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>;
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def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
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"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
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def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
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"true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
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def ExtensionAudio: SubtargetFeature<"audio", "UseAudioOps", "true",
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"Hexagon Audio extension instructions">;
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def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true",
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"Use compound instructions">;
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def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
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@ -68,6 +75,8 @@ def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true",
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"Allow GP-relative addressing of global variables">;
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def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
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"Enable generation of duplex instruction">;
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def FeatureUnsafeFP: SubtargetFeature<"unsafe-fp", "UseUnsafeMath", "true",
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"Use unsafe FP math">;
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def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
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"true", "Reserve register R19">;
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def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim",
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@ -93,11 +102,18 @@ def UseHVXV65 : Predicate<"HST->useHVXV65Ops()">,
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AssemblerPredicate<"ExtensionHVXV65">;
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def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">,
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AssemblerPredicate<"ExtensionHVXV66">;
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def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">,
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AssemblerPredicate<"ExtensionHVXV67">;
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def UseAudio : Predicate<"HST->useAudioOps()">,
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AssemblerPredicate<"ExtensionAudio">;
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def UseZReg : Predicate<"HST->useZRegOps()">,
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AssemblerPredicate<"ExtensionZReg">;
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def UseCompound : Predicate<"HST->useCompound()">;
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def HasPreV65 : Predicate<"HST->hasPreV65()">,
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AssemblerPredicate<"FeatureHasPreV65">;
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def HasMemNoShuf : Predicate<"HST->hasMemNoShuf()">,
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AssemblerPredicate<"FeatureMemNoShuf">;
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def UseUnsafeMath : Predicate<"HST->useUnsafeMath()">;
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def Hvx64: HwMode<"+hvx-length64b">;
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def Hvx128: HwMode<"+hvx-length128b">;
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@ -366,6 +382,10 @@ def : Proc<"hexagonv66", HexagonModelV66,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,
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FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
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FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv67", HexagonModelV67,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
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FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
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FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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37
lib/Target/Hexagon/HexagonArch.h
Normal file
37
lib/Target/Hexagon/HexagonArch.h
Normal file
@ -0,0 +1,37 @@
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//===- HexagonArch.h ------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringRef.h"
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#include "HexagonDepArch.h"
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#include <algorithm>
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namespace llvm {
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namespace Hexagon {
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template <class ArchCont, typename Val>
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bool ValidArch(ArchCont const &ArchList, Val HexArch) {
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return std::any_of(std::begin(ArchList), std::end(ArchList),
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[HexArch](Val V) { return V == HexArch; });
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}
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template <class ArchCont, typename Val>
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llvm::Optional<ArchEnum> GetCpu(ArchCont const &ArchList, Val CPUString) {
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llvm::Optional<ArchEnum> Res;
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auto Entry = ArchList.find(CPUString);
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if (Entry != ArchList.end())
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Res = Entry->second;
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return Res;
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}
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} // namespace Hexagon
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H
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@ -5,15 +5,43 @@
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Automatically generated file, please consult code owner before editing.
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// Automatically generated file, do not edit!
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGON_DEP_ARCH_H
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#define HEXAGON_DEP_ARCH_H
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringRef.h"
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#include <map>
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namespace llvm {
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namespace Hexagon {
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enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66 };
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enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 };
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static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67};
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static constexpr ArrayRef<unsigned> ArchValsNum(ArchValsNumArray);
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static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67" };
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static constexpr ArrayRef<StringLiteral> ArchValsText(ArchValsTextArray);
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static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67" };
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static constexpr ArrayRef<StringLiteral> CpuValsText(CpuValsTextArray);
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static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67" };
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static constexpr ArrayRef<StringLiteral> CpuNickText(CpuNickTextArray);
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static const std::map<std::string, ArchEnum> CpuTable{
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{"generic", Hexagon::ArchEnum::V60},
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{"hexagonv5", Hexagon::ArchEnum::V5},
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{"hexagonv55", Hexagon::ArchEnum::V55},
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{"hexagonv60", Hexagon::ArchEnum::V60},
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{"hexagonv62", Hexagon::ArchEnum::V62},
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{"hexagonv65", Hexagon::ArchEnum::V65},
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{"hexagonv66", Hexagon::ArchEnum::V66},
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{"hexagonv67", Hexagon::ArchEnum::V67},
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};
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} // namespace Hexagon
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} // namespace llvm;
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#endif // HEXAGON_DEP_ARCH_H
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
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@ -5,18 +5,20 @@
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Automatically generated file, please consult code owner before editing.
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// Automatically generated file, do not edit!
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//===----------------------------------------------------------------------===//
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def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexagon V66 architecture">;
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def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<"ArchV66">;
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def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">;
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def HasV65 : Predicate<"HST->hasV65Ops()">, AssemblerPredicate<"ArchV65">;
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def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">;
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def HasV62 : Predicate<"HST->hasV62Ops()">, AssemblerPredicate<"ArchV62">;
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def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">;
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def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<"ArchV60">;
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def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">;
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def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<"ArchV55">;
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def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V5 architecture">;
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def HasV5 : Predicate<"HST->hasV5Ops()">, AssemblerPredicate<"ArchV5">;
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def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">;
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def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<"ArchV55">;
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def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">;
|
||||
def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<"ArchV60">;
|
||||
def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">;
|
||||
def HasV62 : Predicate<"HST->hasV62Ops()">, AssemblerPredicate<"ArchV62">;
|
||||
def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">;
|
||||
def HasV65 : Predicate<"HST->hasV65Ops()">, AssemblerPredicate<"ArchV65">;
|
||||
def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexagon V66 architecture">;
|
||||
def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<"ArchV66">;
|
||||
def ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexagon V67 architecture">;
|
||||
def HasV67 : Predicate<"HST->hasV67Ops()">, AssemblerPredicate<"ArchV67">;
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Automatically generated file, please consult code owner before editing.
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// clang-format off
|
||||
@ -15,24 +15,14 @@
|
||||
#pragma clang diagnostic ignored "-Wunused-function"
|
||||
#endif
|
||||
|
||||
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<4>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<14>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<8>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<7>(MI, tmp, Decoder);
|
||||
signedDecoder<4>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
@ -40,9 +30,9 @@ static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
signedDecoder<12>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<3>(MI, tmp, Decoder);
|
||||
signedDecoder<5>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
@ -50,6 +40,21 @@ static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
signedDecoder<13>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<6>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<14>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<7>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<6>(MI, tmp, Decoder);
|
||||
@ -60,14 +65,19 @@ static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
signedDecoder<9>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
static DecodeStatus s10_6ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<5>(MI, tmp, Decoder);
|
||||
signedDecoder<16>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<6>(MI, tmp, Decoder);
|
||||
signedDecoder<10>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
|
||||
uint64_t, const void *Decoder) {
|
||||
signedDecoder<3>(MI, tmp, Decoder);
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Automatically generated file, please consult code owner before editing.
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def tc_04da405a : InstrItinClass;
|
||||
@ -2554,3 +2554,494 @@ class DepHVXItinV66 {
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>
|
||||
];
|
||||
}
|
||||
|
||||
class DepHVXItinV67 {
|
||||
list<InstrItinData> DepHVXItinV67_list = [
|
||||
InstrItinData <tc_04da405a, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 5],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_05058f6f, /*SLOT1,LOAD,VA_DV*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_05ac6f98, /*SLOT1,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_05ca8cfd, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_08a4f1b6, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_0b04c6c7, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_0ec46cf9, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_131f1c81, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_1381a97c, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [],
|
||||
[]>,
|
||||
|
||||
InstrItinData <tc_15fdf750, /*SLOT23,VS_VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
|
||||
InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_16ff9ef8, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_191381c1, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7],
|
||||
[Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_1ad8a370, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_1ba8a0cd, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_20a4bbec, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [3, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_257f6f7c, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_309dbb4f, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3904b926, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3aacf4a8, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3ce09744, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [1, 2],
|
||||
[Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3e2aaafc, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_447d9895, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_453fe68d, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_46d6c3e0, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_51d0ecc3, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_52447ecc, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_540c3da3, /*SLOT0,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
|
||||
[Hex_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_54a0dc47, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_561aaa58, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_56c4f9fe, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_56e64202, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_58d21193, /*SLOT0,STORE,VA_DV*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_5bf8afbb, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_649072c2, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_660769f1, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_663c80a7, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 3, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_6942b6e0, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_6e7fa133, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_71646d06, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_7177e272, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_718b5c53, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
|
||||
[HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_7273323b, /*SLOT0,STORE,VA_DV*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_7417e785, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_767c4e9d, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [3, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_7e6a3e89, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_8772086c, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_87adc037, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_8e420e4d, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_90bcc1db, /*SLOT2,VX_DV*/
|
||||
[InstrStage<1, [SLOT2], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_946013d8, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_9d1dc972, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_9f363d21, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_a02a10a8, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_ab23f776, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_abe8c3b2, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_ac4046bc, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_af25efd9, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_b091f1c6, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_b28e51aa, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [2],
|
||||
[Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_b4416217, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_b9db8205, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_c0749f3c, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_c127de3a, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_c4edf264, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_c5dba46e, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_c7039829, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_cd94bfe0, /*SLOT23,VS_VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
|
||||
InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_d8287c14, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_db5555f3, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [3],
|
||||
[HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e675c45a, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [1, 2],
|
||||
[Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e8797b98, /*SLOT1,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e99d4c2e, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_f1de44ef, /*SLOT2,VX_DV*/
|
||||
[InstrStage<1, [SLOT2], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_f21e8abb, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_fd7610da, /*SLOT1,LOAD,VA_DV*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>
|
||||
];
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -5,7 +5,7 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Automatically generated file, please consult code owner before editing.
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
namespace llvm {
|
||||
@ -16,49 +16,48 @@ enum Type {
|
||||
TypeALU32_ADDI = 2,
|
||||
TypeALU64 = 3,
|
||||
TypeCJ = 4,
|
||||
TypeCOPROC_VX = 5,
|
||||
TypeCR = 6,
|
||||
TypeCVI_4SLOT_MPY = 7,
|
||||
TypeCVI_GATHER = 8,
|
||||
TypeCVI_GATHER_RST = 9,
|
||||
TypeCVI_HIST = 10,
|
||||
TypeCVI_SCATTER = 11,
|
||||
TypeCVI_SCATTER_DV = 12,
|
||||
TypeCVI_SCATTER_NEW_RST = 13,
|
||||
TypeCVI_SCATTER_NEW_ST = 14,
|
||||
TypeCVI_SCATTER_RST = 15,
|
||||
TypeCVI_VA = 16,
|
||||
TypeCVI_VA_DV = 17,
|
||||
TypeCVI_VINLANESAT = 18,
|
||||
TypeCVI_VM_LD = 19,
|
||||
TypeCVI_VM_NEW_ST = 20,
|
||||
TypeCVI_VM_ST = 21,
|
||||
TypeCVI_VM_STU = 22,
|
||||
TypeCVI_VM_TMP_LD = 23,
|
||||
TypeCVI_VM_VP_LDU = 24,
|
||||
TypeCVI_VP = 25,
|
||||
TypeCVI_VP_VS = 26,
|
||||
TypeCVI_VS = 27,
|
||||
TypeCVI_VS_VX = 28,
|
||||
TypeCVI_VX = 29,
|
||||
TypeCVI_VX_DV = 30,
|
||||
TypeCVI_VX_LATE = 31,
|
||||
TypeCVI_ZW = 32,
|
||||
TypeDUPLEX = 33,
|
||||
TypeENDLOOP = 34,
|
||||
TypeEXTENDER = 35,
|
||||
TypeJ = 36,
|
||||
TypeLD = 37,
|
||||
TypeM = 38,
|
||||
TypeMAPPING = 39,
|
||||
TypeNCJ = 40,
|
||||
TypePSEUDO = 41,
|
||||
TypeST = 42,
|
||||
TypeSUBINSN = 43,
|
||||
TypeS_2op = 44,
|
||||
TypeS_3op = 45,
|
||||
TypeV2LDST = 48,
|
||||
TypeV4LDST = 49,
|
||||
TypeCR = 7,
|
||||
TypeCVI_4SLOT_MPY = 8,
|
||||
TypeCVI_GATHER = 9,
|
||||
TypeCVI_GATHER_DV = 10,
|
||||
TypeCVI_GATHER_RST = 11,
|
||||
TypeCVI_HIST = 12,
|
||||
TypeCVI_SCATTER = 13,
|
||||
TypeCVI_SCATTER_DV = 14,
|
||||
TypeCVI_SCATTER_NEW_RST = 15,
|
||||
TypeCVI_SCATTER_NEW_ST = 16,
|
||||
TypeCVI_SCATTER_RST = 17,
|
||||
TypeCVI_VA = 18,
|
||||
TypeCVI_VA_DV = 19,
|
||||
TypeCVI_VM_LD = 20,
|
||||
TypeCVI_VM_NEW_ST = 21,
|
||||
TypeCVI_VM_ST = 22,
|
||||
TypeCVI_VM_STU = 23,
|
||||
TypeCVI_VM_TMP_LD = 24,
|
||||
TypeCVI_VM_VP_LDU = 25,
|
||||
TypeCVI_VP = 26,
|
||||
TypeCVI_VP_VS = 27,
|
||||
TypeCVI_VS = 28,
|
||||
TypeCVI_VS_VX = 29,
|
||||
TypeCVI_VX = 30,
|
||||
TypeCVI_VX_DV = 31,
|
||||
TypeCVI_VX_LATE = 32,
|
||||
TypeCVI_ZW = 33,
|
||||
TypeDUPLEX = 34,
|
||||
TypeENDLOOP = 35,
|
||||
TypeEXTENDER = 36,
|
||||
TypeJ = 37,
|
||||
TypeLD = 38,
|
||||
TypeM = 39,
|
||||
TypeMAPPING = 40,
|
||||
TypeNCJ = 41,
|
||||
TypePSEUDO = 42,
|
||||
TypeST = 43,
|
||||
TypeSUBINSN = 44,
|
||||
TypeS_2op = 45,
|
||||
TypeS_3op = 46,
|
||||
TypeV2LDST = 49,
|
||||
TypeV4LDST = 50,
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Automatically generated file, please consult code owner before editing.
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class IType<bits<7> t> { bits<7> Value = t; }
|
||||
@ -14,46 +14,45 @@ def TypeALU32_3op : IType<1>;
|
||||
def TypeALU32_ADDI : IType<2>;
|
||||
def TypeALU64 : IType<3>;
|
||||
def TypeCJ : IType<4>;
|
||||
def TypeCOPROC_VX : IType<5>;
|
||||
def TypeCR : IType<6>;
|
||||
def TypeCVI_4SLOT_MPY : IType<7>;
|
||||
def TypeCVI_GATHER : IType<8>;
|
||||
def TypeCVI_GATHER_RST : IType<9>;
|
||||
def TypeCVI_HIST : IType<10>;
|
||||
def TypeCVI_SCATTER : IType<11>;
|
||||
def TypeCVI_SCATTER_DV : IType<12>;
|
||||
def TypeCVI_SCATTER_NEW_RST : IType<13>;
|
||||
def TypeCVI_SCATTER_NEW_ST : IType<14>;
|
||||
def TypeCVI_SCATTER_RST : IType<15>;
|
||||
def TypeCVI_VA : IType<16>;
|
||||
def TypeCVI_VA_DV : IType<17>;
|
||||
def TypeCVI_VINLANESAT : IType<18>;
|
||||
def TypeCVI_VM_LD : IType<19>;
|
||||
def TypeCVI_VM_NEW_ST : IType<20>;
|
||||
def TypeCVI_VM_ST : IType<21>;
|
||||
def TypeCVI_VM_STU : IType<22>;
|
||||
def TypeCVI_VM_TMP_LD : IType<23>;
|
||||
def TypeCVI_VM_VP_LDU : IType<24>;
|
||||
def TypeCVI_VP : IType<25>;
|
||||
def TypeCVI_VP_VS : IType<26>;
|
||||
def TypeCVI_VS : IType<27>;
|
||||
def TypeCVI_VS_VX : IType<28>;
|
||||
def TypeCVI_VX : IType<29>;
|
||||
def TypeCVI_VX_DV : IType<30>;
|
||||
def TypeCVI_VX_LATE : IType<31>;
|
||||
def TypeCVI_ZW : IType<32>;
|
||||
def TypeDUPLEX : IType<33>;
|
||||
def TypeENDLOOP : IType<34>;
|
||||
def TypeEXTENDER : IType<35>;
|
||||
def TypeJ : IType<36>;
|
||||
def TypeLD : IType<37>;
|
||||
def TypeM : IType<38>;
|
||||
def TypeMAPPING : IType<39>;
|
||||
def TypeNCJ : IType<40>;
|
||||
def TypePSEUDO : IType<41>;
|
||||
def TypeST : IType<42>;
|
||||
def TypeSUBINSN : IType<43>;
|
||||
def TypeS_2op : IType<44>;
|
||||
def TypeS_3op : IType<45>;
|
||||
def TypeV2LDST : IType<48>;
|
||||
def TypeV4LDST : IType<49>;
|
||||
def TypeCR : IType<7>;
|
||||
def TypeCVI_4SLOT_MPY : IType<8>;
|
||||
def TypeCVI_GATHER : IType<9>;
|
||||
def TypeCVI_GATHER_DV : IType<10>;
|
||||
def TypeCVI_GATHER_RST : IType<11>;
|
||||
def TypeCVI_HIST : IType<12>;
|
||||
def TypeCVI_SCATTER : IType<13>;
|
||||
def TypeCVI_SCATTER_DV : IType<14>;
|
||||
def TypeCVI_SCATTER_NEW_RST : IType<15>;
|
||||
def TypeCVI_SCATTER_NEW_ST : IType<16>;
|
||||
def TypeCVI_SCATTER_RST : IType<17>;
|
||||
def TypeCVI_VA : IType<18>;
|
||||
def TypeCVI_VA_DV : IType<19>;
|
||||
def TypeCVI_VM_LD : IType<20>;
|
||||
def TypeCVI_VM_NEW_ST : IType<21>;
|
||||
def TypeCVI_VM_ST : IType<22>;
|
||||
def TypeCVI_VM_STU : IType<23>;
|
||||
def TypeCVI_VM_TMP_LD : IType<24>;
|
||||
def TypeCVI_VM_VP_LDU : IType<25>;
|
||||
def TypeCVI_VP : IType<26>;
|
||||
def TypeCVI_VP_VS : IType<27>;
|
||||
def TypeCVI_VS : IType<28>;
|
||||
def TypeCVI_VS_VX : IType<29>;
|
||||
def TypeCVI_VX : IType<30>;
|
||||
def TypeCVI_VX_DV : IType<31>;
|
||||
def TypeCVI_VX_LATE : IType<32>;
|
||||
def TypeCVI_ZW : IType<33>;
|
||||
def TypeDUPLEX : IType<34>;
|
||||
def TypeENDLOOP : IType<35>;
|
||||
def TypeEXTENDER : IType<36>;
|
||||
def TypeJ : IType<37>;
|
||||
def TypeLD : IType<38>;
|
||||
def TypeM : IType<39>;
|
||||
def TypeMAPPING : IType<40>;
|
||||
def TypeNCJ : IType<41>;
|
||||
def TypePSEUDO : IType<42>;
|
||||
def TypeST : IType<43>;
|
||||
def TypeSUBINSN : IType<44>;
|
||||
def TypeS_2op : IType<45>;
|
||||
def TypeS_3op : IType<46>;
|
||||
def TypeV2LDST : IType<49>;
|
||||
def TypeV4LDST : IType<50>;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1728,6 +1728,65 @@ def: Pat<(int_hexagon_F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
def: Pat<(int_hexagon_S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2),
|
||||
(S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV66]>;
|
||||
|
||||
// V67 Scalar Instructions.
|
||||
|
||||
def: Pat<(int_hexagon_M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_vdmpy DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_vdmpy_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_A7_croundd_ri DoubleRegs:$src1, u6_0ImmPred_timm:$src2),
|
||||
(A7_croundd_ri DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_A7_croundd_rr DoubleRegs:$src1, IntRegs:$src2),
|
||||
(A7_croundd_rr DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2),
|
||||
(A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_A7_vclip DoubleRegs:$src1, u5_0ImmPred_timm:$src2),
|
||||
(A7_vclip DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_F2_dfmax DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(F2_dfmax DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_F2_dfmin DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(F2_dfmin DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_F2_dfmpyfix DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(F2_dfmpyfix DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>;
|
||||
def: Pat<(int_hexagon_F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>;
|
||||
|
||||
// V60 HVX Instructions.
|
||||
|
||||
def: Pat<(int_hexagon_V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Automatically generated file, please consult code owner before editing.
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
|
||||
@ -94,6 +94,8 @@ def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= $Rt32", (L4_sub_memopw_
|
||||
def L6_deallocframe_map_to_rawAlias : InstAlias<"deallocframe", (L2_deallocframe D15, R30)>;
|
||||
def L6_return_map_to_rawAlias : InstAlias<"dealloc_return", (L4_return D15, R30)>;
|
||||
def M2_mpyuiAlias : InstAlias<"$Rd32 = mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>;
|
||||
def M7_vdmpyAlias : InstAlias<"$Rdd32 = vdmpyw($Rss32,$Rtt32)", (M7_dcmpyrwc DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
|
||||
def M7_vdmpy_accAlias : InstAlias<"$Rxx32 += vdmpyw($Rss32,$Rtt32)", (M7_dcmpyrwc_acc DoubleRegs:$Rxx32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
|
||||
def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
|
||||
def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
|
||||
def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
|
||||
@ -253,16 +255,9 @@ def V6_vaslwv_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Vv32)", (V6_vaslwv HvxV
|
||||
def V6_vasr_into_altAlias : InstAlias<"$Vxx32 = vasrinto($Vu32,$Vv32)", (V6_vasr_into HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrh_acc_altAlias : InstAlias<"$Vx32 += vasrh($Vu32,$Rt32)", (V6_vasrh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrh_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
def V6_vasrhubsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
def V6_vasrhv_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Vv32)", (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrw_acc_altAlias : InstAlias<"$Vx32 += vasrw($Vu32,$Rt32)", (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrw_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Rt32)", (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrwh_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
def V6_vasrwhsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
def V6_vasrwv_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Vv32)", (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vavgb_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32)", (V6_vavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vavgbrnd_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32):rnd", (V6_vavgbrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
|
||||
2821
lib/Target/Hexagon/HexagonDepMask.h
Normal file
2821
lib/Target/Hexagon/HexagonDepMask.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -5,7 +5,7 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Automatically generated file, please consult code owner before editing.
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass ImmOpPred<code pred, ValueType vt = i32> {
|
||||
@ -13,120 +13,126 @@ multiclass ImmOpPred<code pred, ValueType vt = i32> {
|
||||
def _timm : PatLeaf<(vt timm), pred>;
|
||||
}
|
||||
|
||||
def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
|
||||
defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
|
||||
def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; }
|
||||
defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
|
||||
def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>;
|
||||
def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>;
|
||||
def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; }
|
||||
defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; }
|
||||
defm s8_0ImmPred : ImmOpPred<[{ return isShiftedInt<8, 0>(N->getSExtValue());}]>;
|
||||
def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>;
|
||||
def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>;
|
||||
def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>;
|
||||
def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
|
||||
def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>;
|
||||
def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
|
||||
def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>;
|
||||
def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>;
|
||||
def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>;
|
||||
def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
|
||||
def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
|
||||
def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>;
|
||||
def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; }
|
||||
defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>;
|
||||
def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>;
|
||||
def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>;
|
||||
def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
|
||||
def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
|
||||
defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
|
||||
def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; }
|
||||
defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
|
||||
def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; }
|
||||
defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
|
||||
def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; }
|
||||
defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>;
|
||||
def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; }
|
||||
defm s30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; }
|
||||
defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>;
|
||||
def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; }
|
||||
defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
|
||||
def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; }
|
||||
defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>;
|
||||
def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>;
|
||||
def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>;
|
||||
def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>;
|
||||
def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>;
|
||||
def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>;
|
||||
def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
|
||||
def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>;
|
||||
def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>;
|
||||
def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; }
|
||||
defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
|
||||
def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>;
|
||||
def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; }
|
||||
defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
|
||||
def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; }
|
||||
defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>;
|
||||
def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
|
||||
def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>;
|
||||
def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; }
|
||||
defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>;
|
||||
def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>;
|
||||
def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_1ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>;
|
||||
def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>;
|
||||
def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>;
|
||||
def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>;
|
||||
def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_2Imm : Operand<i32> { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_2ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>;
|
||||
def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>;
|
||||
def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>;
|
||||
def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>;
|
||||
def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
|
||||
def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>;
|
||||
def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>;
|
||||
def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; }
|
||||
defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>;
|
||||
def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
|
||||
defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
|
||||
def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>;
|
||||
def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>;
|
||||
def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; }
|
||||
defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>;
|
||||
def s10_6ImmOperand : AsmOperandClass { let Name = "s10_6Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s10_6Imm : Operand<i32> { let ParserMatchClass = s10_6ImmOperand; let DecoderMethod = "s10_6ImmDecoder"; }
|
||||
defm s10_6ImmPred : ImmOpPred<[{ return isShiftedInt<10, 6>(N->getSExtValue());}]>;
|
||||
def s10_0ImmOperand : AsmOperandClass { let Name = "s10_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s10_0Imm : Operand<i32> { let ParserMatchClass = s10_0ImmOperand; let DecoderMethod = "s10_0ImmDecoder"; }
|
||||
defm s10_0ImmPred : ImmOpPred<[{ return isShiftedInt<10, 0>(N->getSExtValue());}]>;
|
||||
def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; }
|
||||
def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; }
|
||||
defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
|
||||
def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; }
|
||||
def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
|
||||
defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>;
|
||||
|
||||
@ -5,63 +5,58 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Automatically generated file, please consult code owner before editing.
|
||||
// Automatically generated file, do not edit!
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
#ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
|
||||
#define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
|
||||
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H
|
||||
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H
|
||||
|
||||
#include "HexagonInstrInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
inline bool is_TC3x(unsigned SchedClass) {
|
||||
inline bool is_TC1(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_05d3a09b:
|
||||
case Hexagon::Sched::tc_0d8f5752:
|
||||
case Hexagon::Sched::tc_13bfbcf9:
|
||||
case Hexagon::Sched::tc_174516e8:
|
||||
case Hexagon::Sched::tc_1a2fd869:
|
||||
case Hexagon::Sched::tc_1c4528a2:
|
||||
case Hexagon::Sched::tc_32779c6f:
|
||||
case Hexagon::Sched::tc_5b54b33f:
|
||||
case Hexagon::Sched::tc_6b25e783:
|
||||
case Hexagon::Sched::tc_76851da1:
|
||||
case Hexagon::Sched::tc_9debc299:
|
||||
case Hexagon::Sched::tc_a9d88b22:
|
||||
case Hexagon::Sched::tc_bafaade3:
|
||||
case Hexagon::Sched::tc_bcf98408:
|
||||
case Hexagon::Sched::tc_bdceeac1:
|
||||
case Hexagon::Sched::tc_c8ce0b5c:
|
||||
case Hexagon::Sched::tc_d1aa9eaa:
|
||||
case Hexagon::Sched::tc_d773585a:
|
||||
case Hexagon::Sched::tc_df3319ed:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC2early(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_b4407292:
|
||||
case Hexagon::Sched::tc_fc3999b4:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC4x(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_2f7c551d:
|
||||
case Hexagon::Sched::tc_2ff964b4:
|
||||
case Hexagon::Sched::tc_3a867367:
|
||||
case Hexagon::Sched::tc_3b470976:
|
||||
case Hexagon::Sched::tc_4560740b:
|
||||
case Hexagon::Sched::tc_a58fd5cc:
|
||||
case Hexagon::Sched::tc_b8bffe55:
|
||||
case Hexagon::Sched::tc_112d30d6:
|
||||
case Hexagon::Sched::tc_151bf368:
|
||||
case Hexagon::Sched::tc_1c2c7a4a:
|
||||
case Hexagon::Sched::tc_1d41f8b7:
|
||||
case Hexagon::Sched::tc_23708a21:
|
||||
case Hexagon::Sched::tc_24f426ab:
|
||||
case Hexagon::Sched::tc_2f573607:
|
||||
case Hexagon::Sched::tc_388f9897:
|
||||
case Hexagon::Sched::tc_3d14a17b:
|
||||
case Hexagon::Sched::tc_3fbf1042:
|
||||
case Hexagon::Sched::tc_407e96f9:
|
||||
case Hexagon::Sched::tc_42ff66ba:
|
||||
case Hexagon::Sched::tc_4a55d03c:
|
||||
case Hexagon::Sched::tc_5502c366:
|
||||
case Hexagon::Sched::tc_55b33fda:
|
||||
case Hexagon::Sched::tc_56a124a7:
|
||||
case Hexagon::Sched::tc_57a55b54:
|
||||
case Hexagon::Sched::tc_59a7822c:
|
||||
case Hexagon::Sched::tc_5b347363:
|
||||
case Hexagon::Sched::tc_5da50c4b:
|
||||
case Hexagon::Sched::tc_60e324ff:
|
||||
case Hexagon::Sched::tc_651cbe02:
|
||||
case Hexagon::Sched::tc_6fc5dbea:
|
||||
case Hexagon::Sched::tc_711c805f:
|
||||
case Hexagon::Sched::tc_713b66bf:
|
||||
case Hexagon::Sched::tc_9124c04f:
|
||||
case Hexagon::Sched::tc_9c52f549:
|
||||
case Hexagon::Sched::tc_9e27f2f9:
|
||||
case Hexagon::Sched::tc_9f6cd987:
|
||||
case Hexagon::Sched::tc_a1297125:
|
||||
case Hexagon::Sched::tc_a7a13fac:
|
||||
case Hexagon::Sched::tc_b837298f:
|
||||
case Hexagon::Sched::tc_c57d9f39:
|
||||
case Hexagon::Sched::tc_d33e5eee:
|
||||
case Hexagon::Sched::tc_decdde8a:
|
||||
case Hexagon::Sched::tc_ed03645c:
|
||||
case Hexagon::Sched::tc_eeda4109:
|
||||
case Hexagon::Sched::tc_ef921005:
|
||||
case Hexagon::Sched::tc_f999c66e:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
@ -70,72 +65,87 @@ inline bool is_TC4x(unsigned SchedClass) {
|
||||
|
||||
inline bool is_TC2(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_002cb246:
|
||||
case Hexagon::Sched::tc_14b5c689:
|
||||
case Hexagon::Sched::tc_1c80410a:
|
||||
case Hexagon::Sched::tc_4414d8b1:
|
||||
case Hexagon::Sched::tc_6132ba3d:
|
||||
case Hexagon::Sched::tc_61830035:
|
||||
case Hexagon::Sched::tc_679309b8:
|
||||
case Hexagon::Sched::tc_703e822c:
|
||||
case Hexagon::Sched::tc_779080bf:
|
||||
case Hexagon::Sched::tc_784490da:
|
||||
case Hexagon::Sched::tc_88b4f13d:
|
||||
case Hexagon::Sched::tc_9461ff31:
|
||||
case Hexagon::Sched::tc_9e313203:
|
||||
case Hexagon::Sched::tc_a813cf9a:
|
||||
case Hexagon::Sched::tc_bfec0f01:
|
||||
case Hexagon::Sched::tc_cf8126ae:
|
||||
case Hexagon::Sched::tc_d08ee0f4:
|
||||
case Hexagon::Sched::tc_e4a7f9f0:
|
||||
case Hexagon::Sched::tc_f429765c:
|
||||
case Hexagon::Sched::tc_f675fee8:
|
||||
case Hexagon::Sched::tc_f9058dd7:
|
||||
case Hexagon::Sched::tc_01d44cb2:
|
||||
case Hexagon::Sched::tc_0dfac0a7:
|
||||
case Hexagon::Sched::tc_1fcb8495:
|
||||
case Hexagon::Sched::tc_20131976:
|
||||
case Hexagon::Sched::tc_2c13e7f5:
|
||||
case Hexagon::Sched::tc_3edca78f:
|
||||
case Hexagon::Sched::tc_5e4cf0e8:
|
||||
case Hexagon::Sched::tc_65279839:
|
||||
case Hexagon::Sched::tc_7401744f:
|
||||
case Hexagon::Sched::tc_84a7500d:
|
||||
case Hexagon::Sched::tc_8a825db2:
|
||||
case Hexagon::Sched::tc_8b5bd4f5:
|
||||
case Hexagon::Sched::tc_95a33176:
|
||||
case Hexagon::Sched::tc_9b3c0462:
|
||||
case Hexagon::Sched::tc_a08b630b:
|
||||
case Hexagon::Sched::tc_a4e22bbd:
|
||||
case Hexagon::Sched::tc_a7bdb22c:
|
||||
case Hexagon::Sched::tc_bb831a7c:
|
||||
case Hexagon::Sched::tc_c20701f0:
|
||||
case Hexagon::Sched::tc_d3632d88:
|
||||
case Hexagon::Sched::tc_d61dfdc3:
|
||||
case Hexagon::Sched::tc_e3d699e3:
|
||||
case Hexagon::Sched::tc_f098b237:
|
||||
case Hexagon::Sched::tc_f34c1c21:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC1(unsigned SchedClass) {
|
||||
inline bool is_TC3x(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_0663f615:
|
||||
case Hexagon::Sched::tc_0a705168:
|
||||
case Hexagon::Sched::tc_0ae0825c:
|
||||
case Hexagon::Sched::tc_1b6f7cec:
|
||||
case Hexagon::Sched::tc_1fc97744:
|
||||
case Hexagon::Sched::tc_20cdee80:
|
||||
case Hexagon::Sched::tc_2332b92e:
|
||||
case Hexagon::Sched::tc_2eabeebe:
|
||||
case Hexagon::Sched::tc_3d495a39:
|
||||
case Hexagon::Sched::tc_4c5ba658:
|
||||
case Hexagon::Sched::tc_56336eb0:
|
||||
case Hexagon::Sched::tc_56f114f4:
|
||||
case Hexagon::Sched::tc_57890846:
|
||||
case Hexagon::Sched::tc_5a2711e5:
|
||||
case Hexagon::Sched::tc_5b7c0967:
|
||||
case Hexagon::Sched::tc_640086b5:
|
||||
case Hexagon::Sched::tc_643b4717:
|
||||
case Hexagon::Sched::tc_85c9c08f:
|
||||
case Hexagon::Sched::tc_85d5d03f:
|
||||
case Hexagon::Sched::tc_862b3e70:
|
||||
case Hexagon::Sched::tc_946df596:
|
||||
case Hexagon::Sched::tc_9c3ecd83:
|
||||
case Hexagon::Sched::tc_9fc3dae0:
|
||||
case Hexagon::Sched::tc_a1123dda:
|
||||
case Hexagon::Sched::tc_a1c00888:
|
||||
case Hexagon::Sched::tc_ae53734a:
|
||||
case Hexagon::Sched::tc_b31c2e97:
|
||||
case Hexagon::Sched::tc_b4b5c03a:
|
||||
case Hexagon::Sched::tc_b51dc29a:
|
||||
case Hexagon::Sched::tc_cd374165:
|
||||
case Hexagon::Sched::tc_cfd8378a:
|
||||
case Hexagon::Sched::tc_d5b7b0c1:
|
||||
case Hexagon::Sched::tc_d9d43ecb:
|
||||
case Hexagon::Sched::tc_db2bce9c:
|
||||
case Hexagon::Sched::tc_de4df740:
|
||||
case Hexagon::Sched::tc_de554571:
|
||||
case Hexagon::Sched::tc_e78647bd:
|
||||
case Hexagon::Sched::tc_01e1be3b:
|
||||
case Hexagon::Sched::tc_1248597c:
|
||||
case Hexagon::Sched::tc_197dce51:
|
||||
case Hexagon::Sched::tc_28e55c6f:
|
||||
case Hexagon::Sched::tc_2c3e17fc:
|
||||
case Hexagon::Sched::tc_38382228:
|
||||
case Hexagon::Sched::tc_38e0bae9:
|
||||
case Hexagon::Sched::tc_4abdbdc6:
|
||||
case Hexagon::Sched::tc_503ce0f3:
|
||||
case Hexagon::Sched::tc_556f6577:
|
||||
case Hexagon::Sched::tc_5a4b5e58:
|
||||
case Hexagon::Sched::tc_6ae3426b:
|
||||
case Hexagon::Sched::tc_6d861a95:
|
||||
case Hexagon::Sched::tc_788b1d09:
|
||||
case Hexagon::Sched::tc_7f8ae742:
|
||||
case Hexagon::Sched::tc_9406230a:
|
||||
case Hexagon::Sched::tc_a154b476:
|
||||
case Hexagon::Sched::tc_a38c45dc:
|
||||
case Hexagon::Sched::tc_c21d7447:
|
||||
case Hexagon::Sched::tc_d7718fbe:
|
||||
case Hexagon::Sched::tc_db596beb:
|
||||
case Hexagon::Sched::tc_f0cdeccf:
|
||||
case Hexagon::Sched::tc_fae9dfa5:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC2early(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_45f9d1be:
|
||||
case Hexagon::Sched::tc_a4ee89db:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_TC4x(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_02fe1c65:
|
||||
case Hexagon::Sched::tc_0a195f2c:
|
||||
case Hexagon::Sched::tc_7f7f45f5:
|
||||
case Hexagon::Sched::tc_9783714b:
|
||||
case Hexagon::Sched::tc_9e72dc89:
|
||||
case Hexagon::Sched::tc_9edb7c77:
|
||||
case Hexagon::Sched::tc_f0e8e832:
|
||||
case Hexagon::Sched::tc_f7569068:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
@ -143,4 +153,4 @@ inline bool is_TC1(unsigned SchedClass) {
|
||||
}
|
||||
} // namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H
|
||||
|
||||
@ -1762,6 +1762,11 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
|
||||
setOperationAction(ISD::FADD, MVT::f64, Legal);
|
||||
setOperationAction(ISD::FSUB, MVT::f64, Legal);
|
||||
}
|
||||
if (Subtarget.hasV67Ops()) {
|
||||
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
|
||||
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
|
||||
setOperationAction(ISD::FMUL, MVT::f64, Legal);
|
||||
}
|
||||
|
||||
setTargetDAGCombine(ISD::VSELECT);
|
||||
|
||||
|
||||
@ -37,6 +37,8 @@ def HVXVectorAccess : MemAccessSize<5>;
|
||||
// Instruction Class Declaration +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// "Parse" bits are explicity NOT defined in the opcode space to prevent
|
||||
// TableGen from using them for generation of the decoder tables.
|
||||
class OpcodeHexagon {
|
||||
field bits<32> Inst = ?; // Default to an invalid insn.
|
||||
bits<4> IClass = 0; // ICLASS
|
||||
@ -164,6 +166,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
bit CVINew = 0;
|
||||
let TSFlags{62} = CVINew;
|
||||
|
||||
bit isCVI = 0;
|
||||
let TSFlags{63} = isCVI;
|
||||
|
||||
// Fields used for relation models.
|
||||
bit isNonTemporal = 0;
|
||||
string isNT = ""; // set to "true" for non-temporal vector stores.
|
||||
@ -225,10 +230,106 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
|
||||
: InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
|
||||
OpcodeHexagon;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Special Instructions -
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// The 'invalid_decode' instruction is used by the disassembler to
|
||||
// show an instruction that didn't decode correctly. This feature
|
||||
// is only leveraged in a special disassembler mode that's activated
|
||||
// by a command line flag.
|
||||
def tc_invalid : InstrItinClass;
|
||||
class Enc_invalid : OpcodeHexagon {
|
||||
}
|
||||
def invalid_decode : HInst<
|
||||
(outs ),
|
||||
(ins ),
|
||||
"<invalid>",
|
||||
tc_invalid, TypeALU32_2op>, Enc_invalid {
|
||||
let Inst{13-0} = 0b00000000000000;
|
||||
let Inst{31-16} = 0b0000000000000000;
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Duplex Instruction Class Declaration
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class OpcodeDuplex {
|
||||
field bits<32> Inst = ?; // Default to an invalid insn.
|
||||
bits<4> IClass = 0; // ICLASS
|
||||
bits<13> ISubHi = 0; // Low sub-insn
|
||||
bits<13> ISubLo = 0; // High sub-insn
|
||||
|
||||
let Inst{31-29} = IClass{3-1};
|
||||
let Inst{13} = IClass{0};
|
||||
let Inst{15-14} = 0;
|
||||
let Inst{28-16} = ISubHi;
|
||||
let Inst{12-0} = ISubLo;
|
||||
}
|
||||
|
||||
class InstDuplex<bits<4> iClass, list<dag> pattern = [],
|
||||
string cstr = "">
|
||||
: Instruction, OpcodeDuplex {
|
||||
let Namespace = "Hexagon";
|
||||
IType Type = TypeDUPLEX; // uses slot 0,1
|
||||
let isCodeGenOnly = 1;
|
||||
let hasSideEffects = 0;
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins);
|
||||
let IClass = iClass;
|
||||
let Constraints = cstr;
|
||||
let Itinerary = DUPLEX;
|
||||
let Size = 4;
|
||||
|
||||
// SoftFail is a field the disassembler can use to provide a way for
|
||||
// instructions to not match without killing the whole decode process. It is
|
||||
// mainly used for ARM, but Tablegen expects this field to exist or it fails
|
||||
// to build the decode table.
|
||||
field bits<32> SoftFail = 0;
|
||||
|
||||
// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
|
||||
|
||||
let TSFlags{6-0} = Type.Value;
|
||||
|
||||
// Predicated instructions.
|
||||
bits<1> isPredicated = 0;
|
||||
let TSFlags{7} = isPredicated;
|
||||
bits<1> isPredicatedFalse = 0;
|
||||
let TSFlags{8} = isPredicatedFalse;
|
||||
bits<1> isPredicatedNew = 0;
|
||||
let TSFlags{9} = isPredicatedNew;
|
||||
|
||||
// New-value insn helper fields.
|
||||
bits<1> isNewValue = 0;
|
||||
let TSFlags{10} = isNewValue; // New-value consumer insn.
|
||||
bits<1> hasNewValue = 0;
|
||||
let TSFlags{11} = hasNewValue; // New-value producer insn.
|
||||
bits<3> opNewValue = 0;
|
||||
let TSFlags{14-12} = opNewValue; // New-value produced operand.
|
||||
bits<1> isNVStorable = 0;
|
||||
let TSFlags{15} = isNVStorable; // Store that can become new-value store.
|
||||
bits<1> isNVStore = 0;
|
||||
let TSFlags{16} = isNVStore; // New-value store insn.
|
||||
|
||||
// Immediate extender helper fields.
|
||||
bits<1> isExtendable = 0;
|
||||
let TSFlags{17} = isExtendable; // Insn may be extended.
|
||||
bits<1> isExtended = 0;
|
||||
let TSFlags{18} = isExtended; // Insn must be extended.
|
||||
bits<3> opExtendable = 0;
|
||||
let TSFlags{21-19} = opExtendable; // Which operand may be extended.
|
||||
bits<1> isExtentSigned = 0;
|
||||
let TSFlags{22} = isExtentSigned; // Signed or unsigned range.
|
||||
bits<5> opExtentBits = 0;
|
||||
let TSFlags{27-23} = opExtentBits; //Number of bits of range before extending.
|
||||
bits<2> opExtentAlign = 0;
|
||||
let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending.
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction Classes Definitions -
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonInstrFormatsV5.td"
|
||||
include "HexagonInstrFormatsV60.td"
|
||||
include "HexagonInstrFormatsV65.td"
|
||||
|
||||
@ -1,86 +0,0 @@
|
||||
//==- HexagonInstrFormatsV5.td - Hexagon Instruction Formats --*- tablegen -==//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes the Hexagon V5 instruction classes in TableGen format.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Duplex Instruction Class Declaration
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class OpcodeDuplex {
|
||||
field bits<32> Inst = ?; // Default to an invalid insn.
|
||||
bits<4> IClass = 0; // ICLASS
|
||||
bits<13> ISubHi = 0; // Low sub-insn
|
||||
bits<13> ISubLo = 0; // High sub-insn
|
||||
|
||||
let Inst{31-29} = IClass{3-1};
|
||||
let Inst{13} = IClass{0};
|
||||
let Inst{15-14} = 0;
|
||||
let Inst{28-16} = ISubHi;
|
||||
let Inst{12-0} = ISubLo;
|
||||
}
|
||||
|
||||
class InstDuplex<bits<4> iClass, list<dag> pattern = [],
|
||||
string cstr = "">
|
||||
: Instruction, OpcodeDuplex {
|
||||
let Namespace = "Hexagon";
|
||||
IType Type = TypeDUPLEX; // uses slot 0,1
|
||||
let isCodeGenOnly = 1;
|
||||
let hasSideEffects = 0;
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins);
|
||||
let IClass = iClass;
|
||||
let Constraints = cstr;
|
||||
let Itinerary = DUPLEX;
|
||||
let Size = 4;
|
||||
|
||||
// SoftFail is a field the disassembler can use to provide a way for
|
||||
// instructions to not match without killing the whole decode process. It is
|
||||
// mainly used for ARM, but Tablegen expects this field to exist or it fails
|
||||
// to build the decode table.
|
||||
field bits<32> SoftFail = 0;
|
||||
|
||||
// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
|
||||
|
||||
let TSFlags{6-0} = Type.Value;
|
||||
|
||||
// Predicated instructions.
|
||||
bits<1> isPredicated = 0;
|
||||
let TSFlags{7} = isPredicated;
|
||||
bits<1> isPredicatedFalse = 0;
|
||||
let TSFlags{8} = isPredicatedFalse;
|
||||
bits<1> isPredicatedNew = 0;
|
||||
let TSFlags{9} = isPredicatedNew;
|
||||
|
||||
// New-value insn helper fields.
|
||||
bits<1> isNewValue = 0;
|
||||
let TSFlags{10} = isNewValue; // New-value consumer insn.
|
||||
bits<1> hasNewValue = 0;
|
||||
let TSFlags{11} = hasNewValue; // New-value producer insn.
|
||||
bits<3> opNewValue = 0;
|
||||
let TSFlags{14-12} = opNewValue; // New-value produced operand.
|
||||
bits<1> isNVStorable = 0;
|
||||
let TSFlags{15} = isNVStorable; // Store that can become new-value store.
|
||||
bits<1> isNVStore = 0;
|
||||
let TSFlags{16} = isNVStore; // New-value store insn.
|
||||
|
||||
// Immediate extender helper fields.
|
||||
bits<1> isExtendable = 0;
|
||||
let TSFlags{17} = isExtendable; // Insn may be extended.
|
||||
bits<1> isExtended = 0;
|
||||
let TSFlags{18} = isExtended; // Insn must be extended.
|
||||
bits<3> opExtendable = 0;
|
||||
let TSFlags{21-19} = opExtendable; // Which operand may be extended.
|
||||
bits<1> isExtentSigned = 0;
|
||||
let TSFlags{22} = isExtentSigned; // Signed or unsigned range.
|
||||
bits<5> opExtentBits = 0;
|
||||
let TSFlags{27-23} = opExtentBits; //Number of bits of range before extending.
|
||||
bits<2> opExtentAlign = 0;
|
||||
let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending.
|
||||
}
|
||||
@ -923,6 +923,13 @@ let AddedComplexity = 100 in {
|
||||
defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 100, Predicates = [HasV67] in {
|
||||
defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>;
|
||||
defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>;
|
||||
defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>;
|
||||
defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>;
|
||||
}
|
||||
|
||||
defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setgt, v8i1, V8I8>;
|
||||
defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setge, v8i1, V8I8>;
|
||||
defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setgt, v4i1, V4I16>;
|
||||
@ -1408,6 +1415,26 @@ let Predicates = [HasV66] in {
|
||||
def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>;
|
||||
}
|
||||
|
||||
def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt),
|
||||
(F2_dfmpyhh
|
||||
(F2_dfmpylh
|
||||
(F2_dfmpylh
|
||||
(F2_dfmpyll $Rs, $Rt),
|
||||
$Rs, $Rt),
|
||||
$Rt, $Rs),
|
||||
$Rs, $Rt)>;
|
||||
|
||||
let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in {
|
||||
def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>;
|
||||
}
|
||||
let Predicates = [HasV67] in {
|
||||
def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>;
|
||||
def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>;
|
||||
|
||||
def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt),
|
||||
(F2_dfmpyfix $Rt, $Rs))>;
|
||||
}
|
||||
|
||||
// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add,
|
||||
// over add-add with individual multiplies as inputs.
|
||||
let AddedComplexity = 10 in {
|
||||
@ -1634,8 +1661,8 @@ let AddedComplexity = 20, Predicates = [UseCompound] in {
|
||||
(M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>;
|
||||
}
|
||||
|
||||
// Keep these instructions less preferable to M2_macsip/M2_macsin.
|
||||
let Predicates = [UseCompound] in {
|
||||
// Keep these instructions less preferable to M2_macsip/M2_macsin.
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)),
|
||||
(M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>;
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)),
|
||||
@ -1651,7 +1678,6 @@ def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx),
|
||||
def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx),
|
||||
(F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
|
||||
|
||||
|
||||
def: Pat<(mul V2I32:$Rs, V2I32:$Rt),
|
||||
(PS_vmulw V2I32:$Rs, V2I32:$Rt)>;
|
||||
def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)),
|
||||
|
||||
@ -527,13 +527,15 @@ multiclass NewCircularLoad<RegisterClass RC, MemAccessSize MS> {
|
||||
|
||||
let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS],
|
||||
addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
|
||||
// Use timing class of L2_loadrb_pci.
|
||||
def NAME#_pci : LDInst<(outs RC:$Rd32, IntRegs:$Rx32),
|
||||
(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Cs),
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e93a3d71>;
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_5ceb2f9e>;
|
||||
|
||||
// Use timing class of L2_loadrb_pcr.
|
||||
def NAME#_pcr : LDInst<(outs RC:$Rd32, IntRegs:$Rx32),
|
||||
(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Cs),
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_44d3da28>;
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_075c8dd8>;
|
||||
}
|
||||
}
|
||||
|
||||
@ -548,13 +550,15 @@ multiclass NewCircularStore<RegisterClass RC, MemAccessSize MS> {
|
||||
|
||||
let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS],
|
||||
addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
|
||||
// Use timing class of S2_storerb_pci.
|
||||
def NAME#_pci : STInst<(outs IntRegs:$Rx32),
|
||||
(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e86aa961>;
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_b4dc7630>;
|
||||
|
||||
// Use timing class of S2_storerb_pcr.
|
||||
def NAME#_pcr : STInst<(outs IntRegs:$Rx32),
|
||||
(ins IntRegs:$Rx32in, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_da97ee82>;
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_a2b365d2>;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -56,37 +56,14 @@ def tc_ENDLOOP : InstrItinClass;
|
||||
include "HexagonDepIICScalar.td"
|
||||
include "HexagonDepIICHVX.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V5 Machine Info +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonScheduleV5.td"
|
||||
|
||||
// V55 Machine Info +
|
||||
include "HexagonScheduleV55.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V60 Machine Info -
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonIICScalar.td"
|
||||
include "HexagonIICHVX.td"
|
||||
include "HexagonScheduleV60.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V62 Machine Info +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonScheduleV62.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V65 Machine Info +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonScheduleV65.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V66 Machine Info +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonScheduleV66.td"
|
||||
include "HexagonScheduleV67.td"
|
||||
|
||||
39
lib/Target/Hexagon/HexagonScheduleV67.td
Normal file
39
lib/Target/Hexagon/HexagonScheduleV67.td
Normal file
@ -0,0 +1,39 @@
|
||||
//=-HexagonScheduleV67.td - HexagonV67 Scheduling Definitions *- tablegen -*-=//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//
|
||||
// ScalarItin and HVXItin contain some old itineraries
|
||||
// still used by a handful of instructions. Hopefully, we will be able
|
||||
// to get rid of them soon.
|
||||
|
||||
def HexagonV67ItinList : DepScalarItinV66, ScalarItin,
|
||||
DepHVXItinV66, HVXItin, PseudoItin {
|
||||
list<InstrItinData> ItinList =
|
||||
!listconcat(DepScalarItinV66_list, ScalarItin_list,
|
||||
DepHVXItinV66_list, HVXItin_list, PseudoItin_list);
|
||||
}
|
||||
|
||||
def HexagonItinerariesV67 :
|
||||
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
|
||||
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
|
||||
CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
|
||||
CVI_ALL_NOMEM, CVI_ZW],
|
||||
[Hex_FWD, HVX_FWD],
|
||||
HexagonV67ItinList.ItinList>;
|
||||
|
||||
def HexagonModelV67 : SchedMachineModel {
|
||||
// Max issue per cycle == bundle width.
|
||||
let IssueWidth = 4;
|
||||
let Itineraries = HexagonItinerariesV67;
|
||||
let LoadLatency = 1;
|
||||
let CompleteModel = 0;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Hexagon V67 Resource Definitions -
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -90,24 +90,16 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
|
||||
|
||||
HexagonSubtarget &
|
||||
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
|
||||
static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
|
||||
{"generic", Hexagon::ArchEnum::V60},
|
||||
{"hexagonv5", Hexagon::ArchEnum::V5},
|
||||
{"hexagonv55", Hexagon::ArchEnum::V55},
|
||||
{"hexagonv60", Hexagon::ArchEnum::V60},
|
||||
{"hexagonv62", Hexagon::ArchEnum::V62},
|
||||
{"hexagonv65", Hexagon::ArchEnum::V65},
|
||||
{"hexagonv66", Hexagon::ArchEnum::V66},
|
||||
};
|
||||
|
||||
auto FoundIt = CpuTable.find(CPUString);
|
||||
if (FoundIt != CpuTable.end())
|
||||
HexagonArchVersion = FoundIt->second;
|
||||
Optional<Hexagon::ArchEnum> ArchVer =
|
||||
Hexagon::GetCpu(Hexagon::CpuTable, CPUString);
|
||||
if (ArchVer)
|
||||
HexagonArchVersion = *ArchVer;
|
||||
else
|
||||
llvm_unreachable("Unrecognized Hexagon processor version");
|
||||
|
||||
UseHVX128BOps = false;
|
||||
UseHVX64BOps = false;
|
||||
UseAudioOps = false;
|
||||
UseLongCalls = false;
|
||||
|
||||
UseBSBScheduling = hasV60Ops() && EnableBSBSched;
|
||||
|
||||
@ -13,7 +13,7 @@
|
||||
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
|
||||
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
|
||||
|
||||
#include "HexagonDepArch.h"
|
||||
#include "HexagonArch.h"
|
||||
#include "HexagonFrameLowering.h"
|
||||
#include "HexagonISelLowering.h"
|
||||
#include "HexagonInstrInfo.h"
|
||||
@ -45,6 +45,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
|
||||
bool UseHVX64BOps = false;
|
||||
bool UseHVX128BOps = false;
|
||||
|
||||
bool UseAudioOps = false;
|
||||
bool UseCompound = false;
|
||||
bool UseLongCalls = false;
|
||||
bool UseMemops = false;
|
||||
@ -52,6 +53,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
|
||||
bool UseNewValueJumps = false;
|
||||
bool UseNewValueStores = false;
|
||||
bool UseSmallData = false;
|
||||
bool UseUnsafeMath = false;
|
||||
bool UseZRegOps = false;
|
||||
|
||||
bool HasPreV65 = false;
|
||||
@ -165,7 +167,14 @@ public:
|
||||
bool hasV66OpsOnly() const {
|
||||
return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
|
||||
}
|
||||
bool hasV67Ops() const {
|
||||
return getHexagonArchVersion() >= Hexagon::ArchEnum::V67;
|
||||
}
|
||||
bool hasV67OpsOnly() const {
|
||||
return getHexagonArchVersion() == Hexagon::ArchEnum::V67;
|
||||
}
|
||||
|
||||
bool useAudioOps() const { return UseAudioOps; }
|
||||
bool useCompound() const { return UseCompound; }
|
||||
bool useLongCalls() const { return UseLongCalls; }
|
||||
bool useMemops() const { return UseMemops; }
|
||||
@ -173,6 +182,7 @@ public:
|
||||
bool useNewValueJumps() const { return UseNewValueJumps; }
|
||||
bool useNewValueStores() const { return UseNewValueStores; }
|
||||
bool useSmallData() const { return UseSmallData; }
|
||||
bool useUnsafeMath() const { return UseUnsafeMath; }
|
||||
bool useZRegOps() const { return UseZRegOps; }
|
||||
|
||||
bool useHVXOps() const {
|
||||
@ -190,6 +200,9 @@ public:
|
||||
bool useHVXV66Ops() const {
|
||||
return HexagonHVXVersion >= Hexagon::ArchEnum::V66;
|
||||
}
|
||||
bool useHVXV67Ops() const {
|
||||
return HexagonHVXVersion >= Hexagon::ArchEnum::V67;
|
||||
}
|
||||
bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
|
||||
bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
|
||||
|
||||
@ -207,7 +220,11 @@ public:
|
||||
// compiler time and will be removed eventually anyway.
|
||||
bool enableMachineSchedDefaultSched() const override { return false; }
|
||||
|
||||
// For use with PostRAScheduling: get the anti-dependence breaking that should
|
||||
// be performed before post-RA scheduling.
|
||||
AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
|
||||
/// True if the subtarget should run a scheduler after register
|
||||
/// allocation.
|
||||
bool enablePostRAScheduler() const override { return true; }
|
||||
|
||||
bool enableSubRegLiveness() const override;
|
||||
|
||||
@ -237,6 +237,14 @@ HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
|
||||
std::string FS = !FSAttr.hasAttribute(Attribute::None)
|
||||
? FSAttr.getValueAsString().str()
|
||||
: TargetFS;
|
||||
// Append the preexisting target features last, so that +mattr overrides
|
||||
// the "unsafe-fp-math" function attribute.
|
||||
// Creating a separate target feature is not strictly necessary, it only
|
||||
// exists to make "unsafe-fp-math" force creating a new subtarget.
|
||||
|
||||
if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
|
||||
F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
|
||||
FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
|
||||
|
||||
auto &I = SubtargetMap[CPU + FS];
|
||||
if (!I) {
|
||||
|
||||
@ -27,11 +27,6 @@ namespace HexagonII {
|
||||
unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY;
|
||||
unsigned const TypeCVI_LAST = TypeCVI_ZW;
|
||||
|
||||
enum SubTarget {
|
||||
HasV55SubT = 0x3c,
|
||||
HasV60SubT = 0x38,
|
||||
};
|
||||
|
||||
enum AddrMode {
|
||||
NoAddrMode = 0, // No addressing mode
|
||||
Absolute = 1, // Absolute addressing mode
|
||||
@ -165,6 +160,9 @@ namespace HexagonII {
|
||||
|
||||
CVINewPos = 62,
|
||||
CVINewMask = 0x1,
|
||||
|
||||
isCVIPos = 63,
|
||||
isCVIMask = 0x1,
|
||||
};
|
||||
|
||||
// *** The code above must match HexagonInstrFormat*.td *** //
|
||||
|
||||
@ -10,13 +10,13 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "MCTargetDesc/HexagonMCTargetDesc.h"
|
||||
#include "HexagonDepArch.h"
|
||||
#include "HexagonArch.h"
|
||||
#include "HexagonTargetStreamer.h"
|
||||
#include "MCTargetDesc/HexagonInstPrinter.h"
|
||||
#include "MCTargetDesc/HexagonMCAsmInfo.h"
|
||||
#include "MCTargetDesc/HexagonMCELFStreamer.h"
|
||||
#include "MCTargetDesc/HexagonMCInstrInfo.h"
|
||||
#include "MCTargetDesc/HexagonMCTargetDesc.h"
|
||||
#include "TargetInfo/HexagonTargetInfo.h"
|
||||
#include "llvm/ADT/StringExtras.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
@ -39,6 +39,7 @@
|
||||
#include <cstdint>
|
||||
#include <new>
|
||||
#include <string>
|
||||
#include <unordered_map>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -72,6 +73,8 @@ cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
|
||||
cl::init(false));
|
||||
cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
|
||||
cl::init(false));
|
||||
cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
|
||||
cl::init(false));
|
||||
|
||||
cl::opt<Hexagon::ArchEnum>
|
||||
EnableHVX("mhvx",
|
||||
@ -81,6 +84,7 @@ cl::opt<Hexagon::ArchEnum>
|
||||
clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
|
||||
clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
|
||||
clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
|
||||
clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
|
||||
// Sentinel for no value specified.
|
||||
clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
|
||||
// Sentinel for flag not present.
|
||||
@ -107,6 +111,8 @@ static StringRef HexagonGetArchVariant() {
|
||||
return "hexagonv65";
|
||||
if (MV66)
|
||||
return "hexagonv66";
|
||||
if (MV67)
|
||||
return "hexagonv67";
|
||||
return "";
|
||||
}
|
||||
|
||||
@ -168,13 +174,6 @@ unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
|
||||
return (*Lanes = 0, CVI_NONE);
|
||||
}
|
||||
|
||||
namespace llvm {
|
||||
namespace HexagonFUnits {
|
||||
bool isSlot0Only(unsigned units) {
|
||||
return (HexagonItinerariesV62FU::SLOT0 == units);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
@ -345,30 +344,28 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) {
|
||||
case Hexagon::ArchEnum::V66:
|
||||
Result.push_back("+hvxv66");
|
||||
break;
|
||||
case Hexagon::ArchEnum::V67:
|
||||
Result.push_back("+hvxv67");
|
||||
break;
|
||||
case Hexagon::ArchEnum::Generic:{
|
||||
Result.push_back(StringSwitch<StringRef>(CPU)
|
||||
.Case("hexagonv60", "+hvxv60")
|
||||
.Case("hexagonv62", "+hvxv62")
|
||||
.Case("hexagonv65", "+hvxv65")
|
||||
.Case("hexagonv66", "+hvxv66"));
|
||||
.Case("hexagonv66", "+hvxv66")
|
||||
.Case("hexagonv67", "+hvxv67"));
|
||||
break;
|
||||
}
|
||||
case Hexagon::ArchEnum::NoArch:
|
||||
// Sentinal if -mhvx isn't specified
|
||||
// Sentinel if -mhvx isn't specified
|
||||
break;
|
||||
}
|
||||
return join(Result.begin(), Result.end(), ",");
|
||||
}
|
||||
}
|
||||
|
||||
static bool isCPUValid(std::string CPU)
|
||||
{
|
||||
std::vector<std::string> table {
|
||||
"generic", "hexagonv5", "hexagonv55", "hexagonv60",
|
||||
"hexagonv62", "hexagonv65", "hexagonv66",
|
||||
};
|
||||
|
||||
return std::find(table.begin(), table.end(), CPU) != table.end();
|
||||
static bool isCPUValid(const std::string &CPU) {
|
||||
return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend();
|
||||
}
|
||||
|
||||
namespace {
|
||||
@ -387,7 +384,8 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
|
||||
// turns on hvxvNN, corresponding to the existing ArchVNN.
|
||||
FeatureBitset FB = S;
|
||||
unsigned CpuArch = ArchV5;
|
||||
for (unsigned F : {ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
|
||||
for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55,
|
||||
ArchV5}) {
|
||||
if (!FB.test(F))
|
||||
continue;
|
||||
CpuArch = F;
|
||||
@ -402,7 +400,7 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
|
||||
}
|
||||
bool HasHvxVer = false;
|
||||
for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
|
||||
ExtensionHVXV66}) {
|
||||
ExtensionHVXV66, ExtensionHVXV67}) {
|
||||
if (!FB.test(F))
|
||||
continue;
|
||||
HasHvxVer = true;
|
||||
@ -415,6 +413,9 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
|
||||
|
||||
// HasHvxVer is false, and UseHvx is true.
|
||||
switch (CpuArch) {
|
||||
case ArchV67:
|
||||
FB.set(ExtensionHVXV67);
|
||||
LLVM_FALLTHROUGH;
|
||||
case ArchV66:
|
||||
FB.set(ExtensionHVXV66);
|
||||
LLVM_FALLTHROUGH;
|
||||
@ -438,19 +439,34 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
|
||||
StringRef CPUName = Features.first;
|
||||
StringRef ArchFS = Features.second;
|
||||
|
||||
MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
|
||||
|
||||
if (CPU.equals("help"))
|
||||
exit(0);
|
||||
|
||||
if (!isCPUValid(CPUName.str())) {
|
||||
errs() << "error: invalid CPU \"" << CPUName.str().c_str()
|
||||
<< "\" specified\n";
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
|
||||
if (HexagonDisableDuplex) {
|
||||
llvm::FeatureBitset Features = X->getFeatureBits();
|
||||
X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
|
||||
}
|
||||
|
||||
X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
|
||||
|
||||
// The Z-buffer instructions are grandfathered in for current
|
||||
// architectures but omitted for new ones. Future instruction
|
||||
// sets may introduce new/conflicting z-buffer instructions.
|
||||
const bool ZRegOnDefault =
|
||||
(CPUName == "hexagonv67") || (CPUName == "hexagonv66");
|
||||
if (ZRegOnDefault) {
|
||||
llvm::FeatureBitset Features = X->getFeatureBits();
|
||||
X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
|
||||
}
|
||||
|
||||
return X;
|
||||
}
|
||||
|
||||
@ -462,6 +478,7 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
|
||||
{"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
|
||||
{"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
|
||||
{"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
|
||||
{"hexagonv67", ELF::EF_HEXAGON_MACH_V67},
|
||||
};
|
||||
|
||||
auto F = ElfFlags.find(STI.getCPU());
|
||||
@ -486,6 +503,10 @@ public:
|
||||
|
||||
bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
|
||||
uint64_t Size, uint64_t &Target) const override {
|
||||
if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
|
||||
isConditionalBranch(Inst)))
|
||||
return false;
|
||||
|
||||
//assert(!HexagonMCInstrInfo::isBundle(Inst));
|
||||
if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
|
||||
return false;
|
||||
|
||||
@ -458,6 +458,7 @@ HexagonShuffler::HexagonPacketSummary HexagonShuffler::GetPacketSummary() {
|
||||
case HexagonII::TypeCVI_VM_LD:
|
||||
case HexagonII::TypeCVI_VM_TMP_LD:
|
||||
case HexagonII::TypeCVI_GATHER:
|
||||
case HexagonII::TypeCVI_GATHER_DV:
|
||||
case HexagonII::TypeCVI_GATHER_RST:
|
||||
++Summary.NonZCVIloads;
|
||||
LLVM_FALLTHROUGH;
|
||||
|
||||
67
test/CodeGen/Hexagon/df-min-max.ll
Normal file
67
test/CodeGen/Hexagon/df-min-max.ll
Normal file
@ -0,0 +1,67 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: df_min_olt:
|
||||
; CHECK: dfmin
|
||||
define double @df_min_olt(double %x, double %y) #0 {
|
||||
%t = fcmp olt double %x, %y
|
||||
%u = select i1 %t, double %x, double %y
|
||||
ret double %u
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_min_ole:
|
||||
; CHECK: dfmin
|
||||
define double @df_min_ole(double %x, double %y) #0 {
|
||||
%t = fcmp ole double %x, %y
|
||||
%u = select i1 %t, double %x, double %y
|
||||
ret double %u
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_max_ogt:
|
||||
; CHECK: dfmax
|
||||
define double @df_max_ogt(double %x, double %y) #0 {
|
||||
%t = fcmp ogt double %x, %y
|
||||
%u = select i1 %t, double %x, double %y
|
||||
ret double %u
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_max_oge:
|
||||
; CHECK: dfmax
|
||||
define double @df_max_oge(double %x, double %y) #0 {
|
||||
%t = fcmp oge double %x, %y
|
||||
%u = select i1 %t, double %x, double %y
|
||||
ret double %u
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_max_olt:
|
||||
; CHECK: dfmax
|
||||
define double @df_max_olt(double %x, double %y) #0 {
|
||||
%t = fcmp olt double %x, %y
|
||||
%u = select i1 %t, double %y, double %x
|
||||
ret double %u
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_max_ole:
|
||||
; CHECK: dfmax
|
||||
define double @df_max_ole(double %x, double %y) #0 {
|
||||
%t = fcmp ole double %x, %y
|
||||
%u = select i1 %t, double %y, double %x
|
||||
ret double %u
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_min_ogt:
|
||||
; CHECK: dfmin
|
||||
define double @df_min_ogt(double %x, double %y) #0 {
|
||||
%t = fcmp ogt double %x, %y
|
||||
%u = select i1 %t, double %y, double %x
|
||||
ret double %u
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_min_oge:
|
||||
; CHECK: dfmin
|
||||
define double @df_min_oge(double %x, double %y) #0 {
|
||||
%t = fcmp oge double %x, %y
|
||||
%u = select i1 %t, double %y, double %x
|
||||
ret double %u
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="hexagonv67" }
|
||||
45
test/CodeGen/Hexagon/fminmax-v67.ll
Normal file
45
test/CodeGen/Hexagon/fminmax-v67.ll
Normal file
@ -0,0 +1,45 @@
|
||||
; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=hexagonv67 < %s | FileCheck %s
|
||||
|
||||
|
||||
; CHECK-LABEL: t1
|
||||
; CHECK: dfmax
|
||||
|
||||
define dso_local double @t1(double %a, double %b) local_unnamed_addr {
|
||||
entry:
|
||||
%0 = tail call double @llvm.maxnum.f64(double %a, double %b)
|
||||
ret double %0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: t2
|
||||
; CHECK: dfmin
|
||||
|
||||
define dso_local double @t2(double %a, double %b) local_unnamed_addr {
|
||||
entry:
|
||||
%0 = tail call double @llvm.minnum.f64(double %a, double %b)
|
||||
ret double %0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: t3
|
||||
; CHECK: sfmax
|
||||
|
||||
define dso_local float @t3(float %a, float %b) local_unnamed_addr {
|
||||
entry:
|
||||
%0 = tail call float @llvm.maxnum.f32(float %a, float %b)
|
||||
ret float %0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: t4
|
||||
; CHECK: sfmin
|
||||
|
||||
define dso_local float @t4(float %a, float %b) local_unnamed_addr {
|
||||
entry:
|
||||
%0 = tail call float @llvm.minnum.f32(float %a, float %b)
|
||||
ret float %0
|
||||
}
|
||||
|
||||
declare double @llvm.minnum.f64(double, double) #1
|
||||
declare double @llvm.maxnum.f64(double, double) #1
|
||||
declare float @llvm.maxnum.f32(float, float) #1
|
||||
declare float @llvm.minnum.f32(float, float) #1
|
||||
|
||||
attributes #1 = { nounwind readnone speculatable }
|
||||
52
test/CodeGen/Hexagon/fmul-v67.ll
Normal file
52
test/CodeGen/Hexagon/fmul-v67.ll
Normal file
@ -0,0 +1,52 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
|
||||
; CHECK-LABEL: test_00:
|
||||
; CHECK: sfmpy(r0,r1)
|
||||
define float @test_00(float %a0, float %a1) #0 {
|
||||
b2:
|
||||
%v3 = fmul float %a0, %a1
|
||||
ret float %v3
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_01:
|
||||
; CHECK-DAG: [[R10:(r[0-9]+:[0-9]+)]] = dfmpyfix(r1:0,r3:2)
|
||||
; CHECK-DAG: [[R11:(r[0-9]+:[0-9]+)]] = dfmpyfix(r3:2,r1:0)
|
||||
; CHECK: [[R12:(r[0-9]+:[0-9]+)]] = dfmpyll([[R10]],[[R11]])
|
||||
; CHECK: [[R12]] += dfmpylh([[R10]],[[R11]])
|
||||
; CHECK: [[R12]] += dfmpylh([[R11]],[[R10]])
|
||||
; CHECK: [[R12]] += dfmpyhh([[R10]],[[R11]])
|
||||
define double @test_01(double %a0, double %a1) #1 {
|
||||
b2:
|
||||
%v3 = fmul double %a0, %a1
|
||||
ret double %v3
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_02:
|
||||
; CHECK-DAG: [[R20:(r[0-9]+:[0-9]+)]] = dfmpyfix(r1:0,r3:2)
|
||||
; CHECK-DAG: [[R21:(r[0-9]+:[0-9]+)]] = dfmpyfix(r3:2,r1:0)
|
||||
; CHECK: [[R22:(r[0-9]+:[0-9]+)]] = dfmpyll([[R20]],[[R21]])
|
||||
; CHECK: [[R22]] += dfmpylh([[R20]],[[R21]])
|
||||
; CHECK: [[R22]] += dfmpylh([[R21]],[[R20]])
|
||||
; CHECK: [[R22]] += dfmpyhh([[R20]],[[R21]])
|
||||
define double @test_02(double %a0, double %a1) #2 {
|
||||
b2:
|
||||
%v3 = fmul double %a0, %a1
|
||||
ret double %v3
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_03:
|
||||
; CHECK: [[R30:(r[0-9]+:[0-9]+)]] = dfmpyll(r1:0,r3:2)
|
||||
; CHECK: [[R30]] += dfmpylh(r1:0,r3:2)
|
||||
; CHECK: [[R30]] += dfmpylh(r3:2,r1:0)
|
||||
; CHECK: [[R30]] += dfmpyhh(r1:0,r3:2)
|
||||
define double @test_03(double %a0, double %a1) #3 {
|
||||
b2:
|
||||
%v3 = fmul double %a0, %a1
|
||||
ret double %v3
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind "target-cpu"="hexagonv67" }
|
||||
attributes #2 = { nounwind "target-cpu"="hexagonv67" "unsafe-fp-math"="false" }
|
||||
attributes #3 = { nounwind "target-cpu"="hexagonv67" "unsafe-fp-math"="true" }
|
||||
285
test/CodeGen/Hexagon/intrinsics-v67.ll
Normal file
285
test/CodeGen/Hexagon/intrinsics-v67.ll
Normal file
@ -0,0 +1,285 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: @t1
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} += dfmpylh(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
|
||||
define dso_local double @t1(double %a, double %b, double %c) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call double @llvm.hexagon.F2.dfmpylh(double %a, double %b, double %c) #2
|
||||
ret double %0
|
||||
}
|
||||
|
||||
declare double @llvm.hexagon.F2.dfmpylh(double, double, double) #1
|
||||
|
||||
; CHECK-LABEL: @t2
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} += dfmpyhh(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
|
||||
define dso_local double @t2(double %a, double %b, double %c) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call double @llvm.hexagon.F2.dfmpyhh(double %a, double %b, double %c) #2
|
||||
ret double %0
|
||||
}
|
||||
|
||||
declare double @llvm.hexagon.F2.dfmpyhh(double, double, double) #1
|
||||
|
||||
; CHECK-LABEL: @t3
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmax(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
|
||||
define dso_local double @t3(double %a, double %b) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call double @llvm.hexagon.F2.dfmax(double %a, double %b) #2
|
||||
ret double %0
|
||||
}
|
||||
|
||||
declare double @llvm.hexagon.F2.dfmax(double, double) #1
|
||||
|
||||
; CHECK-LABEL: @t4
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmin(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
|
||||
define dso_local double @t4(double %a, double %b) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call double @llvm.hexagon.F2.dfmin(double %a, double %b) #2
|
||||
ret double %0
|
||||
}
|
||||
|
||||
declare double @llvm.hexagon.F2.dfmin(double, double) #1
|
||||
|
||||
; CHECK-LABEL: @t5
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmpyfix(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
|
||||
define dso_local double @t5(double %a, double %b) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call double @llvm.hexagon.F2.dfmpyfix(double %a, double %b) #2
|
||||
ret double %0
|
||||
}
|
||||
|
||||
declare double @llvm.hexagon.F2.dfmpyfix(double, double) #1
|
||||
|
||||
; CHECK-LABEL: @t6
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmpyll(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
|
||||
define dso_local double @t6(double %a, double %b) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call double @llvm.hexagon.F2.dfmpyll(double %a, double %b) #2
|
||||
ret double %0
|
||||
}
|
||||
|
||||
declare double @llvm.hexagon.F2.dfmpyll(double, double) #1
|
||||
|
||||
; CHECK-LABEL: @t7
|
||||
; CHECK:r{{[0-9]+}}:{{[0-9]+}} = cmpyrw(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}}*)
|
||||
define dso_local i64 @t7(i64 %a, i64 %b) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.vdmpy(i64 %a, i64 %b)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.vdmpy(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t8
|
||||
; CHECK:r{{[0-9]+}}:{{[0-9]+}} += cmpyrw(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}}*)
|
||||
define dso_local i64 @t8(i64 %a, i64 %b, i64 %c) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.vdmpy.acc(i64 %a, i64 %b, i64 %c)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.vdmpy.acc(i64, i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t9
|
||||
; CHECK: r1:0 = cmpyrw(r1:0,r3:2)
|
||||
define i64 @t9(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyrw(i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyrw(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t10
|
||||
; CHECK: r1:0 += cmpyrw(r3:2,r5:4)
|
||||
define i64 @t10(i64 %rxx, i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyrw.acc(i64 %rxx, i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyrw.acc(i64, i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t11
|
||||
; CHECK: r1:0 = cmpyrw(r1:0,r3:2*)
|
||||
define i64 @t11(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyrwc(i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyrwc(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t12
|
||||
; CHECK: r1:0 += cmpyrw(r3:2,r5:4*)
|
||||
define i64 @t12(i64 %rxx, i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %rxx, i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64, i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t13
|
||||
; CHECK: r1:0 = cmpyiw(r1:0,r3:2)
|
||||
define i64 @t13(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyiw(i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyiw(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t14
|
||||
; CHECK: r1:0 += cmpyiw(r3:2,r5:4)
|
||||
define i64 @t14(i64 %rxx, i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyiw.acc(i64 %rxx, i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyiw.acc(i64, i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t15
|
||||
; CHECK: r1:0 = cmpyiw(r1:0,r3:2*)
|
||||
define i64 @t15(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyiwc(i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyiwc(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t16
|
||||
; CHECK: r1:0 += cmpyiw(r3:2,r5:4*)
|
||||
define i64 @t16(i64 %rxx, i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.M7.dcmpyiwc.acc(i64 %rxx, i64 %rss, i64 %rtt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.M7.dcmpyiwc.acc(i64, i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t17
|
||||
; CHECK: r0 = cmpyrw(r1:0,r3:2):<<1:sat
|
||||
define i32 @t17(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyrw(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyrw(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t18
|
||||
; CHECK: r0 = cmpyrw(r1:0,r3:2*):<<1:sat
|
||||
define i32 @t18(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyrwc(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyrwc(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t19
|
||||
; CHECK: r0 = cmpyiw(r1:0,r3:2):<<1:sat
|
||||
define i32 @t19(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyiw(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyiw(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t20
|
||||
; CHECK: r0 = cmpyiw(r1:0,r3:2*):<<1:sat
|
||||
define i32 @t20(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyiwc(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyiwc(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t21
|
||||
; CHECK: r0 = cmpyrw(r1:0,r3:2):<<1:rnd:sat
|
||||
define i32 @t21(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyrw.rnd(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyrw.rnd(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t22
|
||||
; CHECK: r0 = cmpyrw(r1:0,r3:2*):<<1:rnd:sat
|
||||
define i32 @t22(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyrwc.rnd(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyrwc.rnd(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t23
|
||||
; CHECK: r0 = cmpyiw(r1:0,r3:2):<<1:rnd:sat
|
||||
define i32 @t23(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyiw.rnd(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyiw.rnd(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t24
|
||||
; CHECK: r0 = cmpyiw(r1:0,r3:2*):<<1:rnd:sat
|
||||
define i32 @t24(i64 %rss, i64 %rtt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.M7.wcmpyiwc.rnd(i64 %rss, i64 %rtt)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.M7.wcmpyiwc.rnd(i64, i64) #1
|
||||
|
||||
; CHECK-LABEL: @t25
|
||||
; CHECK: r1:0 = cround(r1:0,#0)
|
||||
define i64 @t25(i64 %rss) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.A7.croundd.ri(i64 %rss, i32 0)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.A7.croundd.ri(i64, i32) #1
|
||||
|
||||
; CHECK-LABEL: @t26
|
||||
; CHECK: r1:0 = cround(r1:0,r2)
|
||||
define i64 @t26(i64 %rss, i32 %rt) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.A7.croundd.rr(i64 %rss, i32 %rt)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.A7.croundd.rr(i64, i32) #1
|
||||
|
||||
; CHECK-LABEL: @t27
|
||||
; CHECK: r0 = clip(r0,#0)
|
||||
define i32 @t27(i32 %rs) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i32 @llvm.hexagon.A7.clip(i32 %rs, i32 0)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.A7.clip(i32, i32) #1
|
||||
|
||||
; CHECK-LABEL: @t28
|
||||
; CHECK: r1:0 = vclip(r1:0,#0)
|
||||
define i64 @t28(i64 %rs) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.hexagon.A7.vclip(i64 %rs, i32 0)
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.A7.vclip(i64, i32) #1
|
||||
|
||||
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv67" "target-features"="-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { readnone }
|
||||
attributes #2 = { nounwind }
|
||||
@ -24,7 +24,6 @@
|
||||
; CHECK: }
|
||||
; CHECK: }
|
||||
; CHECK: }
|
||||
; CHECK-NOT: }
|
||||
; CHECK: }{{[ \t]*}}:endloop
|
||||
|
||||
@g0 = external constant [10 x i16], align 128
|
||||
@ -199,5 +198,5 @@ b8: ; preds = %b7, %b0
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
|
||||
attributes #1 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" }
|
||||
attributes #2 = { nounwind }
|
||||
|
||||
2810
test/MC/Hexagon/extensions/v67_hvx.s
Normal file
2810
test/MC/Hexagon/extensions/v67_hvx.s
Normal file
File diff suppressed because it is too large
Load Diff
4
test/MC/Hexagon/v67.s
Normal file
4
test/MC/Hexagon/v67.s
Normal file
@ -0,0 +1,4 @@
|
||||
# RUN: llvm-mc -arch=hexagon -mv67 -mattr=+hvx,+hvx-length128B -filetype=obj %s | llvm-objdump -mhvx=v66 -d - | FileCheck %s
|
||||
|
||||
# CHECK: 1a81e0e2 { v2.uw = vrotr(v0.uw,v1.uw) }
|
||||
v2.uw=vrotr(v0.uw, v1.uw)
|
||||
10
test/MC/Hexagon/v67_all.s
Normal file
10
test/MC/Hexagon/v67_all.s
Normal file
@ -0,0 +1,10 @@
|
||||
# RUN: llvm-mc -arch=hexagon -mv67 -mhvx -filetype=obj %s | llvm-objdump -mhvx=v66 -d - | FileCheck %s
|
||||
|
||||
# CHECK: { v3:0.w = vrmpyz(v0.b,r0.ub) }
|
||||
V3:0.w=vrmpyz(v0.b,r0.ub)
|
||||
# CHECK: { v3:0.w += vrmpyz(v0.b,r0.ub) }
|
||||
V3:0.w+=vrmpyz(v0.b,r0.ub)
|
||||
# CHECK: { v3:0.w = vrmpyz(v0.b,r0.ub++) }
|
||||
V3:0.w=vrmpyz(v0.b,r0.ub++)
|
||||
# CHECK: { v3:0.w += vrmpyz(v0.b,r0.ub++) }
|
||||
V3:0.w+=vrmpyz(v0.b,r0.ub++)
|
||||
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Block a user