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[PowerPC] Generate pre-increment floating-point ld/st instructions

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PowerPC supports pre-increment floating-point load/store instructions, both r+r
and r+i, and we had patterns for them, but they were not marked as legal. Mark
them as legal (and add a test case).

llvm-svn: 228327
This commit is contained in:
Hal Finkel 2015-02-05 18:42:53 +00:00
parent a65b414ebc
commit 3efdfb5daa
2 changed files with 44 additions and 0 deletions
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4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -88,11 +88,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
if (Subtarget.useCRBits()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);

40
test/CodeGen/PowerPC/flt-preinc.ll Normal file
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@ -0,0 +1,40 @@
; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readonly
define float @tf(float* nocapture readonly %i, i32 signext %o) #0 {
entry:
%idx.ext = sext i32 %o to i64
%add.ptr = getelementptr inbounds float* %i, i64 %idx.ext
%0 = load float* %add.ptr, align 4
%add.ptr.sum = add nsw i64 %idx.ext, 1
%add.ptr3 = getelementptr inbounds float* %i, i64 %add.ptr.sum
%1 = load float* %add.ptr3, align 4
%add = fadd float %0, %1
ret float %add
; CHECK-LABEL: @tf
; CHECK: lfsux
; CHECK: blr
}
; Function Attrs: nounwind readonly
define double @td(double* nocapture readonly %i, i32 signext %o) #0 {
entry:
%idx.ext = sext i32 %o to i64
%add.ptr = getelementptr inbounds double* %i, i64 %idx.ext
%0 = load double* %add.ptr, align 8
%add.ptr.sum = add nsw i64 %idx.ext, 1
%add.ptr3 = getelementptr inbounds double* %i, i64 %add.ptr.sum
%1 = load double* %add.ptr3, align 8
%add = fadd double %0, %1
ret double %add
; CHECK-LABEL: @td
; CHECK: lfdux
; CHECK: blr
}
attributes #0 = { nounwind readonly }