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[AArch64] Lower fptrunc/fpext from/to FP128t to/from FP16

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The compiler-rt part which adds the emitted symbols is handled in
a subsequent patch.

Differential Revision: https://reviews.llvm.org/D91731
This commit is contained in:
Adhemerval Zanella 2020-11-18 17:21:46 +00:00
parent 8270667b76
commit 3f1ee6c0a7
4 changed files with 19 additions and 0 deletions
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1
include/llvm/IR/RuntimeLibcalls.def
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@ -286,6 +286,7 @@ HANDLE_LIBCALL(FPEXT_F64_PPCF128, "__gcc_dtoq")
HANDLE_LIBCALL(FPEXT_F80_F128, "__extendxftf2") HANDLE_LIBCALL(FPEXT_F80_F128, "__extendxftf2")
HANDLE_LIBCALL(FPEXT_F64_F128, "__extenddftf2") HANDLE_LIBCALL(FPEXT_F64_F128, "__extenddftf2")
HANDLE_LIBCALL(FPEXT_F32_F128, "__extendsftf2") HANDLE_LIBCALL(FPEXT_F32_F128, "__extendsftf2")
HANDLE_LIBCALL(FPEXT_F16_F128, "__extendhftf2")
HANDLE_LIBCALL(FPEXT_F32_F64, "__extendsfdf2") HANDLE_LIBCALL(FPEXT_F32_F64, "__extendsfdf2")
HANDLE_LIBCALL(FPEXT_F16_F32, "__gnu_h2f_ieee") HANDLE_LIBCALL(FPEXT_F16_F32, "__gnu_h2f_ieee")
HANDLE_LIBCALL(FPROUND_F32_F16, "__gnu_f2h_ieee") HANDLE_LIBCALL(FPROUND_F32_F16, "__gnu_f2h_ieee")

2
lib/CodeGen/TargetLoweringBase.cpp
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@ -224,6 +224,8 @@ RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
if (OpVT == MVT::f16) { if (OpVT == MVT::f16) {
if (RetVT == MVT::f32) if (RetVT == MVT::f32)
return FPEXT_F16_F32; return FPEXT_F16_F32;
if (RetVT == MVT::f128)
return FPEXT_F16_F128;
} else if (OpVT == MVT::f32) { } else if (OpVT == MVT::f32) {
if (RetVT == MVT::f64) if (RetVT == MVT::f64)
return FPEXT_F32_F64; return FPEXT_F32_F64;

2
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -417,8 +417,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom); setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom); setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom); setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom); setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom); setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);

14
test/CodeGen/AArch64/arm64-fp128.ll
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@ -219,6 +219,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
; CHECK: ret ; CHECK: ret
} }
@varhalf = global half 0.0, align 2
@varfloat = global float 0.0, align 4 @varfloat = global float 0.0, align 4
@vardouble = global double 0.0, align 8 @vardouble = global double 0.0, align 8
@ -227,6 +228,12 @@ define void @test_round() {
%val = load fp128, fp128* @lhs, align 16 %val = load fp128, fp128* @lhs, align 16
%half = fptrunc fp128 %val to half
store half %half, half* @varhalf, align 2
; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
; CHECK: bl __trunctfhf2
; CHECK: str h0, [{{x[0-9]+}}, :lo12:varhalf]
%float = fptrunc fp128 %val to float %float = fptrunc fp128 %val to float
store float %float, float* @varfloat, align 4 store float %float, float* @varfloat, align 4
; CHECK: bl __trunctfsf2 ; CHECK: bl __trunctfsf2
@ -245,6 +252,13 @@ define void @test_extend() {
%val = load fp128, fp128* @lhs, align 16 %val = load fp128, fp128* @lhs, align 16
%half = load half, half* @varhalf
%fromhalf = fpext half %half to fp128
store volatile fp128 %fromhalf, fp128* @lhs, align 16
; CHECK: ldr h0, [{{x[0-9]+}}, :lo12:varhalf]
; CHECK: bl __extendhftf2
; CHECK: str q0, [{{x[0-9]+}}, :lo12:lhs]
%float = load float, float* @varfloat %float = load float, float* @varfloat
%fromfloat = fpext float %float to fp128 %fromfloat = fpext float %float to fp128
store volatile fp128 %fromfloat, fp128* @lhs, align 16 store volatile fp128 %fromfloat, fp128* @lhs, align 16