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[AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9
GFX9 should select opsel version. Differential Revision: https://reviews.llvm.org/D44279 llvm-svn: 327106
This commit is contained in:
Stanislav Mekhanoshin
parent
a8cf642b8a
commit
3f3b8a51e0
@ -406,16 +406,16 @@ def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
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} // End SubtargetPredicate = isCIVI
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let SubtargetPredicate = Has16BitInsts in {
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let renamedInGFX9 = 1 in {
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def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
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def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> {
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let Predicates = [Has16BitInsts, isVIOnly];
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}
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let SubtargetPredicate = isGFX9 in {
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def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
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def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9",
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VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> {
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let renamedInGFX9 = 1;
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let Predicates = [Has16BitInsts, isGFX9];
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}
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let isCommutable = 1 in {
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let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
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let renamedInGFX9 = 1 in {
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def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
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@ -436,8 +436,7 @@ def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f1
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def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
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def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
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} // End isCommutable = 1
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} // End SubtargetPredicate = Has16BitInsts
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} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
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let SubtargetPredicate = isVI in {
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def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
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@ -695,7 +694,7 @@ multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
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let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
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multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
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def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
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def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
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VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
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VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
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let AsmString = AsmName # ps.AsmOperands;
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@ -703,7 +702,7 @@ multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
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}
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multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
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def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
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def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
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VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
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VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
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let AsmString = AsmName # ps.AsmOperands;
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@ -711,7 +710,7 @@ multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
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}
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multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
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def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
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def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
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VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
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VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
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let AsmString = AsmName # ps.AsmOperands;
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@ -719,7 +718,7 @@ multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName>
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}
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multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
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def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
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def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
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VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
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VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
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let AsmString = AsmName # ps.AsmOperands;
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@ -1,6 +1,7 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=+fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=+fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8_9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8_9 %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8_9 %s
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; Make sure fdiv is promoted to f32.
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@ -20,17 +21,17 @@
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; SI: v_div_fixup_f32
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; SI: v_cvt_f16_f32
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; GFX8_9: {{flat|global}}_load_ushort [[LHS:v[0-9]+]]
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; GFX8_9: {{flat|global}}_load_ushort [[RHS:v[0-9]+]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_LHS:v[0-9]+]], [[LHS]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_RHS:v[0-9]+]], [[RHS]]
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; GFX8_9-DAG: v_cvt_f32_f16_e32 [[CVT_LHS:v[0-9]+]], [[LHS]]
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; GFX8_9-DAG: v_cvt_f32_f16_e32 [[CVT_RHS:v[0-9]+]], [[RHS]]
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; VI-DAG: v_rcp_f32_e32 [[RCP_RHS:v[0-9]+]], [[CVT_RHS]]
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; VI: v_mul_f32_e32 [[MUL:v[0-9]+]], [[CVT_LHS]], [[RCP_RHS]]
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; VI: v_cvt_f16_f32_e32 [[CVT_BACK:v[0-9]+]], [[MUL]]
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; VI: v_div_fixup_f16 [[RESULT:v[0-9]+]], [[CVT_BACK]], [[RHS]], [[LHS]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9-DAG: v_rcp_f32_e32 [[RCP_RHS:v[0-9]+]], [[CVT_RHS]]
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; GFX8_9: v_mul_f32_e32 [[MUL:v[0-9]+]], [[CVT_LHS]], [[RCP_RHS]]
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; GFX8_9: v_cvt_f16_f32_e32 [[CVT_BACK:v[0-9]+]], [[MUL]]
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; GFX8_9: v_div_fixup_f16 [[RESULT:v[0-9]+]], [[CVT_BACK]], [[RHS]], [[LHS]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_fdiv_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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@ -49,11 +50,11 @@ entry:
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}
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; GCN-LABEL: {{^}}v_rcp_f16:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [[RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_load_ushort [[VAL:v[0-9]+]]
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; GFX8_9-NOT: [[VAL]]
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; GFX8_9: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; GFX8_9-NOT: [[RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_rcp_f16(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -67,11 +68,11 @@ entry:
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}
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; GCN-LABEL: {{^}}v_rcp_f16_abs:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e64 [[RESULT:v[0-9]+]], |[[VAL]]|
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_load_ushort [[VAL:v[0-9]+]]
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; GFX8_9-NOT: [[VAL]]
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; GFX8_9: v_rcp_f16_e64 [[RESULT:v[0-9]+]], |[[VAL]]|
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; GFX8_9-NOT: [RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_rcp_f16_abs(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -86,11 +87,11 @@ entry:
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}
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; GCN-LABEL: {{^}}v_rcp_f16_arcp:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [[RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_load_ushort [[VAL:v[0-9]+]]
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; GFX8_9-NOT: [[VAL]]
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; GFX8_9: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; GFX8_9-NOT: [[RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_rcp_f16_arcp(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -104,11 +105,11 @@ entry:
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}
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; GCN-LABEL: {{^}}v_rcp_f16_neg:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[VAL]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_load_ushort [[VAL:v[0-9]+]]
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; GFX8_9-NOT: [[VAL]]
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; GFX8_9: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[VAL]]
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; GFX8_9-NOT: [RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_rcp_f16_neg(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -122,11 +123,11 @@ entry:
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}
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; GCN-LABEL: {{^}}v_rsq_f16:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rsq_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_load_ushort [[VAL:v[0-9]+]]
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; GFX8_9-NOT: [[VAL]]
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; GFX8_9: v_rsq_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; GFX8_9-NOT: [RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_rsq_f16(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -141,12 +142,12 @@ entry:
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}
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; GCN-LABEL: {{^}}v_rsq_f16_neg:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_sqrt_f16_e32 [[SQRT:v[0-9]+]], [[VAL]]
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; VI-NEXT: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[SQRT]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_load_ushort [[VAL:v[0-9]+]]
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; GFX8_9-NOT: [[VAL]]
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; GFX8_9: v_sqrt_f16_e32 [[SQRT:v[0-9]+]], [[VAL]]
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; GFX8_9-NEXT: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[SQRT]]
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; GFX8_9-NOT: [RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_rsq_f16_neg(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -161,13 +162,13 @@ entry:
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}
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; GCN-LABEL: {{^}}v_fdiv_f16_arcp:
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; GFX8_9: {{flat|global}}_load_ushort [[LHS:v[0-9]+]]
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; GFX8_9: {{flat|global}}_load_ushort [[RHS:v[0-9]+]]
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; VI: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; VI: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
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; GFX8_9: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; GFX8_9: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_fdiv_f16_arcp(half addrspace(1)* %r, half addrspace(1)* %a, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -183,13 +184,13 @@ entry:
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}
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; GCN-LABEL: {{^}}v_fdiv_f16_unsafe:
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; GFX8_9: {{flat|global}}_load_ushort [[LHS:v[0-9]+]]
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; GFX8_9: {{flat|global}}_load_ushort [[RHS:v[0-9]+]]
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; VI: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; VI: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
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; GFX8_9: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; GFX8_9: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_fdiv_f16_unsafe(half addrspace(1)* %r, half addrspace(1)* %a, half addrspace(1)* %b) #2 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -207,8 +208,8 @@ entry:
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; FUNC-LABEL: {{^}}div_arcp_2_x_pat_f16:
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; SI: v_mul_f32_e32 v{{[0-9]+}}, 0.5, v{{[0-9]+}}
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; VI: v_mul_f16_e32 [[MUL:v[0-9]+]], 0.5, v{{[0-9]+}}
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; VI: buffer_store_short [[MUL]]
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; GFX8_9: v_mul_f16_e32 [[MUL:v[0-9]+]], 0.5, v{{[0-9]+}}
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; GFX8_9: buffer_store_short [[MUL]]
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define amdgpu_kernel void @div_arcp_2_x_pat_f16(half addrspace(1)* %out) #0 {
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%x = load half, half addrspace(1)* undef
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%rcp = fdiv arcp half %x, 2.0
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@ -219,8 +220,8 @@ define amdgpu_kernel void @div_arcp_2_x_pat_f16(half addrspace(1)* %out) #0 {
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; FUNC-LABEL: {{^}}div_arcp_k_x_pat_f16:
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; SI: v_mul_f32_e32 v{{[0-9]+}}, 0x3dcccccd, v{{[0-9]+}}
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; VI: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x2e66, v{{[0-9]+}}
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; VI: buffer_store_short [[MUL]]
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; GFX8_9: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x2e66, v{{[0-9]+}}
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; GFX8_9: buffer_store_short [[MUL]]
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define amdgpu_kernel void @div_arcp_k_x_pat_f16(half addrspace(1)* %out) #0 {
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%x = load half, half addrspace(1)* undef
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%rcp = fdiv arcp half %x, 10.0
|
||||
@ -231,8 +232,8 @@ define amdgpu_kernel void @div_arcp_k_x_pat_f16(half addrspace(1)* %out) #0 {
|
||||
; FUNC-LABEL: {{^}}div_arcp_neg_k_x_pat_f16:
|
||||
; SI: v_mul_f32_e32 v{{[0-9]+}}, 0xbdcccccd, v{{[0-9]+}}
|
||||
|
||||
; VI: v_mul_f16_e32 [[MUL:v[0-9]+]], 0xae66, v{{[0-9]+}}
|
||||
; VI: buffer_store_short [[MUL]]
|
||||
; GFX8_9: v_mul_f16_e32 [[MUL:v[0-9]+]], 0xae66, v{{[0-9]+}}
|
||||
; GFX8_9: buffer_store_short [[MUL]]
|
||||
define amdgpu_kernel void @div_arcp_neg_k_x_pat_f16(half addrspace(1)* %out) #0 {
|
||||
%x = load half, half addrspace(1)* undef
|
||||
%rcp = fdiv arcp half %x, -10.0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user