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Add missing test update from 3e5ce49
Sorry for the build break, apparently forgot to build ARM target.
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@ -180,8 +180,7 @@ define void @test_stride2_4i32(i32* readonly %data, i32* noalias nocapture %dst,
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP6:!llvm.loop !.*]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[END:%.*]], label [[SCALAR_PH]]
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; CHECK-NEXT: br label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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@ -196,7 +195,7 @@ define void @test_stride2_4i32(i32* readonly %data, i32* noalias nocapture %dst,
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; CHECK-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX9]], align 4
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; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_023]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[END]], label [[FOR_BODY]], [[LOOP7:!llvm.loop !.*]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[END:%.*]], label [[FOR_BODY]], [[LOOP7:!llvm.loop !.*]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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