From 3f9a40fa378445dc6d32083910294a0313c08eb9 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 13 Sep 2016 18:33:29 +0000 Subject: [PATCH] [DAGCombiner] Use APInt directly in (shl (zext (srl x, C)), C) combine range test To avoid assertion, we must ensure that the inner shift constant is within range before calling ConstantSDNode::getZExtValue(). We already know that the outer shift constant is in range. Followup to D23007 llvm-svn: 281362 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++-- test/CodeGen/X86/shift-i128.ll | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c449c7d4070..269a55357aa 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4545,8 +4545,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) { N0.getOperand(0).getOpcode() == ISD::SRL) { SDValue N0Op0 = N0.getOperand(0); if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) { - uint64_t c1 = N0Op0C1->getZExtValue(); - if (c1 < VT.getScalarSizeInBits()) { + if (N0Op0C1->getAPIntValue().ult(VT.getScalarSizeInBits())) { + uint64_t c1 = N0Op0C1->getZExtValue(); uint64_t c2 = N1C->getZExtValue(); if (c1 == c2) { SDValue NewOp0 = N0.getOperand(0); diff --git a/test/CodeGen/X86/shift-i128.ll b/test/CodeGen/X86/shift-i128.ll index 1de99b15e42..265a051bb1b 100644 --- a/test/CodeGen/X86/shift-i128.ll +++ b/test/CodeGen/X86/shift-i128.ll @@ -134,3 +134,10 @@ define <2 x i256> @shl_zext_shl_outofrange(<2 x i128> %a0) { %3 = shl <2 x i256> %2, ret <2 x i256> %3 } + +define <2 x i256> @shl_zext_lshr_outofrange(<2 x i128> %a0) { + %1 = lshr <2 x i128> %a0, + %2 = zext <2 x i128> %1 to <2 x i256> + %3 = shl <2 x i256> %2, + ret <2 x i256> %3 +}