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[AArch64][SVE] Implement structured store intrinsics
Summary:
This patch adds initial support for the following intrinsics:
* llvm.aarch64.sve.st2
* llvm.aarch64.sve.st3
* llvm.aarch64.sve.st4
For storing two, three and four vectors worth of data. Basic codegen for
reg+immediate forms are implemented. Reg+reg addressing modes will be
addressed in a later patch.
These intrinsics are intended for use in the Arm C Language Extension
(ACLE).
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D75947
This commit is contained in:
Cullen Rhodes
parent
74a8dfdced
commit
4020b155d6
@ -790,6 +790,25 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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LLVMPointerToElt<0>],
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[IntrArgMemOnly, NoCapture<2>]>;
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class AdvSIMD_2Vec_PredStore_Intrinsic
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: Intrinsic<[],
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[llvm_anyvector_ty, LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerTo<0>],
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[IntrArgMemOnly, NoCapture<3>]>;
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class AdvSIMD_3Vec_PredStore_Intrinsic
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: Intrinsic<[],
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[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerTo<0>],
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[IntrArgMemOnly, NoCapture<4>]>;
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class AdvSIMD_4Vec_PredStore_Intrinsic
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: Intrinsic<[],
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[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerTo<0>],
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[IntrArgMemOnly, NoCapture<5>]>;
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class AdvSIMD_SVE_Index_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMVectorElementType<0>,
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@ -1293,6 +1312,9 @@ def int_aarch64_sve_ldff1 : AdvSIMD_1Vec_PredLoad_Intrinsic;
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//
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def int_aarch64_sve_st1 : AdvSIMD_1Vec_PredStore_Intrinsic;
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def int_aarch64_sve_st2 : AdvSIMD_2Vec_PredStore_Intrinsic;
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def int_aarch64_sve_st3 : AdvSIMD_3Vec_PredStore_Intrinsic;
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def int_aarch64_sve_st4 : AdvSIMD_4Vec_PredStore_Intrinsic;
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def int_aarch64_sve_stnt1 : AdvSIMD_1Vec_PredStore_Intrinsic;
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@ -223,6 +223,9 @@ public:
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/// unchanged; otherwise a REG_SEQUENCE value is returned.
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SDValue createDTuple(ArrayRef<SDValue> Vecs);
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SDValue createQTuple(ArrayRef<SDValue> Vecs);
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// Form a sequence of SVE registers for instructions using list of vectors,
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// e.g. structured loads and stores (ldN, stN).
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SDValue createZTuple(ArrayRef<SDValue> Vecs);
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/// Generic helper for the createDTuple/createQTuple
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/// functions. Those should almost always be called instead.
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@ -258,6 +261,7 @@ public:
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void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectPredicatedStore(SDNode *N, unsigned NumVecs, const unsigned Opc);
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bool tryBitfieldExtractOp(SDNode *N);
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bool tryBitfieldExtractOpFromSExt(SDNode *N);
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@ -1192,6 +1196,16 @@ SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
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return createTuple(Regs, RegClassIDs, SubRegs);
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}
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SDValue AArch64DAGToDAGISel::createZTuple(ArrayRef<SDValue> Regs) {
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static const unsigned RegClassIDs[] = {AArch64::ZPR2RegClassID,
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AArch64::ZPR3RegClassID,
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AArch64::ZPR4RegClassID};
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static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1,
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AArch64::zsub2, AArch64::zsub3};
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return createTuple(Regs, RegClassIDs, SubRegs);
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}
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SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
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const unsigned RegClassIDs[],
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const unsigned SubRegs[]) {
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@ -1414,6 +1428,23 @@ void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
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ReplaceNode(N, St);
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}
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void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
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const unsigned Opc) {
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SDLoc dl(N);
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// Form a REG_SEQUENCE to force register allocation.
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SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
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SDValue RegSeq = createZTuple(Regs);
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SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
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N->getOperand(NumVecs + 3), // address
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CurDAG->getTargetConstant(0, dl, MVT::i64), // offset
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N->getOperand(0)}; // chain
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SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
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ReplaceNode(N, St);
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}
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bool AArch64DAGToDAGISel::SelectAddrModeFrameIndexSVE(SDValue N, SDValue &Base,
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SDValue &OffImm) {
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SDLoc dl(N);
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@ -3877,6 +3908,54 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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}
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break;
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}
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case Intrinsic::aarch64_sve_st2: {
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if (VT == MVT::nxv16i8) {
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SelectPredicatedStore(Node, 2, AArch64::ST2B_IMM);
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return;
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} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16) {
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SelectPredicatedStore(Node, 2, AArch64::ST2H_IMM);
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return;
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} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
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SelectPredicatedStore(Node, 2, AArch64::ST2W_IMM);
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return;
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} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
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SelectPredicatedStore(Node, 2, AArch64::ST2D_IMM);
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return;
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}
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break;
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}
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case Intrinsic::aarch64_sve_st3: {
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if (VT == MVT::nxv16i8) {
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SelectPredicatedStore(Node, 3, AArch64::ST3B_IMM);
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return;
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} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16) {
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SelectPredicatedStore(Node, 3, AArch64::ST3H_IMM);
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return;
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} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
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SelectPredicatedStore(Node, 3, AArch64::ST3W_IMM);
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return;
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} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
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SelectPredicatedStore(Node, 3, AArch64::ST3D_IMM);
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return;
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}
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break;
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}
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case Intrinsic::aarch64_sve_st4: {
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if (VT == MVT::nxv16i8) {
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SelectPredicatedStore(Node, 4, AArch64::ST4B_IMM);
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return;
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} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16) {
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SelectPredicatedStore(Node, 4, AArch64::ST4H_IMM);
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return;
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} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
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SelectPredicatedStore(Node, 4, AArch64::ST4W_IMM);
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return;
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} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
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SelectPredicatedStore(Node, 4, AArch64::ST4D_IMM);
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return;
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}
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break;
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}
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}
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break;
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}
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@ -1,5 +1,305 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; ST2B
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;
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define void @st2b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st2b_i8:
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; CHECK: st2b { z0.b, z1.b }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %addr)
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ret void
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}
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;
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; ST2H
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;
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define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
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; CHECK-LABEL: st2h_i16:
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; CHECK: st2h { z0.h, z1.h }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
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<vscale x 8 x i16> %v1,
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<vscale x 8 x i1> %pred,
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<vscale x 8 x i16>* %addr)
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ret void
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}
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define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
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; CHECK-LABEL: st2h_f16:
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; CHECK: st2h { z0.h, z1.h }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
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<vscale x 8 x half> %v1,
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<vscale x 8 x i1> %pred,
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<vscale x 8 x half>* %addr)
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ret void
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}
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;
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; ST2W
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;
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define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
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; CHECK-LABEL: st2w_i32:
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; CHECK: st2w { z0.s, z1.s }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
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<vscale x 4 x i32> %v1,
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<vscale x 4 x i1> %pred,
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<vscale x 4 x i32>* %addr)
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ret void
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}
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define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
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; CHECK-LABEL: st2w_f32:
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; CHECK: st2w { z0.s, z1.s }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
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<vscale x 4 x float> %v1,
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<vscale x 4 x i1> %pred,
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<vscale x 4 x float>* %addr)
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ret void
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}
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;
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; ST2D
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;
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define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
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; CHECK-LABEL: st2d_i64:
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; CHECK: st2d { z0.d, z1.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
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<vscale x 2 x i64> %v1,
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<vscale x 2 x i1> %pred,
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<vscale x 2 x i64>* %addr)
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ret void
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}
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define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
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; CHECK-LABEL: st2d_f64:
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; CHECK: st2d { z0.d, z1.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
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<vscale x 2 x double> %v1,
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<vscale x 2 x i1> %pred,
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<vscale x 2 x double>* %addr)
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ret void
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}
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;
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; ST3B
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;
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define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st3b_i8:
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; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i8> %v2,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %addr)
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ret void
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}
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;
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; ST3H
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;
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define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
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; CHECK-LABEL: st3h_i16:
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; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
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<vscale x 8 x i16> %v1,
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<vscale x 8 x i16> %v2,
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<vscale x 8 x i1> %pred,
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<vscale x 8 x i16>* %addr)
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ret void
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}
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define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
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; CHECK-LABEL: st3h_f16:
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; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
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<vscale x 8 x half> %v1,
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<vscale x 8 x half> %v2,
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<vscale x 8 x i1> %pred,
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<vscale x 8 x half>* %addr)
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ret void
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}
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;
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; ST3W
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;
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define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
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; CHECK-LABEL: st3w_i32:
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; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
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<vscale x 4 x i32> %v1,
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<vscale x 4 x i32> %v2,
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<vscale x 4 x i1> %pred,
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<vscale x 4 x i32>* %addr)
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ret void
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}
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define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
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; CHECK-LABEL: st3w_f32:
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; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
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<vscale x 4 x float> %v1,
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<vscale x 4 x float> %v2,
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<vscale x 4 x i1> %pred,
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<vscale x 4 x float>* %addr)
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ret void
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}
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;
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; ST3D
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;
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define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
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; CHECK-LABEL: st3d_i64:
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; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
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<vscale x 2 x i64> %v1,
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<vscale x 2 x i64> %v2,
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<vscale x 2 x i1> %pred,
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<vscale x 2 x i64>* %addr)
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ret void
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}
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define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
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; CHECK-LABEL: st3d_f64:
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; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
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<vscale x 2 x double> %v1,
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<vscale x 2 x double> %v2,
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<vscale x 2 x i1> %pred,
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<vscale x 2 x double>* %addr)
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ret void
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}
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;
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; ST4B
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;
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define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st4b_i8:
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; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
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; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4H
|
||||
;
|
||||
|
||||
define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
|
||||
; CHECK-LABEL: st4h_i16:
|
||||
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
|
||||
<vscale x 8 x i16> %v1,
|
||||
<vscale x 8 x i16> %v2,
|
||||
<vscale x 8 x i16> %v3,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x i16>* %addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
|
||||
; CHECK-LABEL: st4h_f16:
|
||||
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
|
||||
<vscale x 8 x half> %v1,
|
||||
<vscale x 8 x half> %v2,
|
||||
<vscale x 8 x half> %v3,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x half>* %addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4W
|
||||
;
|
||||
|
||||
define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
|
||||
; CHECK-LABEL: st4w_i32:
|
||||
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
|
||||
<vscale x 4 x i32> %v1,
|
||||
<vscale x 4 x i32> %v2,
|
||||
<vscale x 4 x i32> %v3,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x i32>* %addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
|
||||
; CHECK-LABEL: st4w_f32:
|
||||
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
|
||||
<vscale x 4 x float> %v1,
|
||||
<vscale x 4 x float> %v2,
|
||||
<vscale x 4 x float> %v3,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x float>* %addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4D
|
||||
;
|
||||
|
||||
define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
|
||||
; CHECK-LABEL: st4d_i64:
|
||||
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
|
||||
<vscale x 2 x i64> %v1,
|
||||
<vscale x 2 x i64> %v2,
|
||||
<vscale x 2 x i64> %v3,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x i64>* %addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
|
||||
; CHECK-LABEL: st4d_f64:
|
||||
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
|
||||
<vscale x 2 x double> %v1,
|
||||
<vscale x 2 x double> %v2,
|
||||
<vscale x 2 x double> %v3,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x double>* %addr)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; STNT1B
|
||||
;
|
||||
@ -86,6 +386,31 @@ define void @stnt1d_f64(<vscale x 2 x double> %data, <vscale x 2 x i1> %pred, do
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
||||
declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
||||
declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
||||
declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
|
||||
declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
|
||||
declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user