RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

Add definitions of 64-bit loads and stores. Add a patterns for unaligned

Browse Source 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
This commit is contained in:
Akira Hatanaka 2011-10-11 00:27:28 +00:00
parent cb617ae8e0
commit 404fb72f59
3 changed files with 38 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -167,6 +167,29 @@ let Predicates = [HasMips64r2] in {
def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
}
/// Load and Store Instructions
/// aligned
defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>;
defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>;
defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>;
defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>;
defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>;
defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>;
defm LD : LoadM64<0x37, "ld", load_a>;
defm SD : StoreM64<0x3f, "sd", store_a>;
/// unaligned
defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>;
defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>;
defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>;
defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
defm ULD : LoadM64<0x37, "uld", load_u, 1>;
defm USD : StoreM64<0x3f, "usd", store_u, 1>;
/// Multiply and Divide Instructions.
def DMULT : Mul64<0x1c, "dmult", IIImul>;
def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
@ -198,3 +221,9 @@ def : Pat<(i64 immSExt16:$in),
(DADDiu ZERO_64, imm:$in)>;
def : Pat<(i64 immZExt16:$in),
(DORi ZERO_64, imm:$in)>;
// zextloadi32_u
def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
Requires<[IsN64]>;
def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
Requires<[NotN64]>;

2
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -232,7 +232,7 @@ MipsTargetLowering(MipsTargetMachine &TM)
bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
return SVT == MVT::i32 || SVT == MVT::i16;
return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16;
}
EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {

8
lib/Target/Mips/MipsInstrInfo.td
View File

@ -226,14 +226,22 @@ def sextloadi16_a : AlignedLoad<sextloadi16>;
def zextloadi16_a : AlignedLoad<zextloadi16>;
def extloadi16_a : AlignedLoad<extloadi16>;
def load_a : AlignedLoad<load>;
def sextloadi32_a : AlignedLoad<sextloadi32>;
def zextloadi32_a : AlignedLoad<zextloadi32>;
def extloadi32_a : AlignedLoad<extloadi32>;
def truncstorei16_a : AlignedStore<truncstorei16>;
def store_a : AlignedStore<store>;
def truncstorei32_a : AlignedStore<truncstorei32>;
def sextloadi16_u : UnalignedLoad<sextloadi16>;
def zextloadi16_u : UnalignedLoad<zextloadi16>;
def extloadi16_u : UnalignedLoad<extloadi16>;
def load_u : UnalignedLoad<load>;
def sextloadi32_u : UnalignedLoad<sextloadi32>;
def zextloadi32_u : UnalignedLoad<zextloadi32>;
def extloadi32_u : UnalignedLoad<extloadi32>;
def truncstorei16_u : UnalignedStore<truncstorei16>;
def store_u : UnalignedStore<store>;
def truncstorei32_u : UnalignedStore<truncstorei32>;
//===----------------------------------------------------------------------===//
// Instructions specific format