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[MIPS GlobalISel] Select G_SELECT
Add widen scalar for type index 1 (i1 condition) for G_SELECT. Select G_SELECT for pointer, s32(integer) and smaller low level types on MIPS32. Differential Revision: https://reviews.llvm.org/D56001 llvm-svn: 350063
This commit is contained in:
Petar Avramovic
parent
9c2bbe2344
commit
40620da2b2
@ -777,15 +777,18 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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return Legalized;
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case TargetOpcode::G_SELECT:
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if (TypeIdx != 0)
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return UnableToLegalize;
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// Perform operation at larger width (any extension is fine here, high bits
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// don't affect the result) and then truncate the result back to the
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// original type.
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Observer.changingInstr(MI);
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widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
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widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
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widenScalarDst(MI, WideTy);
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if (TypeIdx == 0) {
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// Perform operation at larger width (any extension is fine here, high
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// bits don't affect the result) and then truncate the result back to the
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// original type.
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widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
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widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
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widenScalarDst(MI, WideTy);
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} else {
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// Explicit extension is required here since high bits affect the result.
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widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
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}
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Observer.changedInstr(MI);
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return Legalized;
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@ -172,6 +172,15 @@ bool MipsInstructionSelector::select(MachineInstr &I,
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I.eraseFromParent();
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return true;
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}
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case G_SELECT: {
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// Handle operands with pointer type.
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
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.add(I.getOperand(0))
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.add(I.getOperand(2))
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.add(I.getOperand(1))
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.add(I.getOperand(3));
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break;
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}
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case G_CONSTANT: {
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int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
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unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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@ -35,6 +35,11 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalForCartesianProduct({p0, s32}, {p0});
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getActionDefinitionsBuilder(G_SELECT)
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.legalForCartesianProduct({p0, s32}, {s32})
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.minScalar(0, s32)
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.minScalar(1, s32);
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getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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@ -111,6 +111,13 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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&Mips::ValueMappings[Mips::GPRIdx],
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&Mips::ValueMappings[Mips::GPRIdx]});
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break;
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case G_SELECT:
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OperandsMapping =
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getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
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&Mips::ValueMappings[Mips::GPRIdx],
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&Mips::ValueMappings[Mips::GPRIdx],
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&Mips::ValueMappings[Mips::GPRIdx]});
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break;
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default:
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return getInvalidInstructionMapping();
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}
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72
test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
Normal file
72
test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
Normal file
@ -0,0 +1,72 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @select_i32() {entry: ret void}
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define void @select_ptr() {entry: ret void}
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...
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---
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name: select_i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; MIPS32-LABEL: name: select_i32
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
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; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
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; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
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; MIPS32: $v0 = COPY [[MOVN_I_I]]
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; MIPS32: RetRA implicit $v0
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%3:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = COPY $a2
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%6:gprb(s32) = G_CONSTANT i32 1
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%7:gprb(s32) = COPY %3(s32)
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%5:gprb(s32) = G_AND %7, %6
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%4:gprb(s32) = G_SELECT %5(s32), %1, %2
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$v0 = COPY %4(s32)
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RetRA implicit $v0
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...
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---
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name: select_ptr
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; MIPS32-LABEL: name: select_ptr
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
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; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
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; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
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; MIPS32: $v0 = COPY [[MOVN_I_I]]
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; MIPS32: RetRA implicit $v0
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%3:gprb(s32) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%6:gprb(s32) = G_CONSTANT i32 1
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%7:gprb(s32) = COPY %3(s32)
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%5:gprb(s32) = G_AND %7, %6
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%4:gprb(p0) = G_SELECT %5(s32), %1, %2
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$v0 = COPY %4(p0)
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RetRA implicit $v0
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...
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172
test/CodeGen/Mips/GlobalISel/legalizer/select.mir
Normal file
172
test/CodeGen/Mips/GlobalISel/legalizer/select.mir
Normal file
@ -0,0 +1,172 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @select_i8() {entry: ret void}
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define void @select_i16() {entry: ret void}
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define void @select_i32() {entry: ret void}
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define void @select_ptr() {entry: ret void}
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define void @select_with_negation() {entry: ret void}
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...
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---
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name: select_i8
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; MIPS32-LABEL: name: select_i8
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]]
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; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
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; MIPS32: $v0 = COPY [[COPY6]](s32)
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; MIPS32: RetRA implicit $v0
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%3:_(s32) = COPY $a0
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%0:_(s1) = G_TRUNC %3(s32)
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%4:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %4(s32)
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%5:_(s32) = COPY $a2
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%2:_(s8) = G_TRUNC %5(s32)
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%6:_(s8) = G_SELECT %0(s1), %1, %2
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%7:_(s32) = G_ANYEXT %6(s8)
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$v0 = COPY %7(s32)
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RetRA implicit $v0
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...
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---
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name: select_i16
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; MIPS32-LABEL: name: select_i16
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]]
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; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
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; MIPS32: $v0 = COPY [[COPY6]](s32)
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; MIPS32: RetRA implicit $v0
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%3:_(s32) = COPY $a0
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%0:_(s1) = G_TRUNC %3(s32)
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%4:_(s32) = COPY $a1
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%1:_(s16) = G_TRUNC %4(s32)
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%5:_(s32) = COPY $a2
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%2:_(s16) = G_TRUNC %5(s32)
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%6:_(s16) = G_SELECT %0(s1), %1, %2
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%7:_(s32) = G_ANYEXT %6(s16)
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$v0 = COPY %7(s32)
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RetRA implicit $v0
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...
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---
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name: select_i32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; MIPS32-LABEL: name: select_i32
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
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; MIPS32: $v0 = COPY [[SELECT]](s32)
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; MIPS32: RetRA implicit $v0
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%3:_(s32) = COPY $a0
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%0:_(s1) = G_TRUNC %3(s32)
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%1:_(s32) = COPY $a1
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%2:_(s32) = COPY $a2
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%4:_(s32) = G_SELECT %0(s1), %1, %2
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$v0 = COPY %4(s32)
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RetRA implicit $v0
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...
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---
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name: select_ptr
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; MIPS32-LABEL: name: select_ptr
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
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; MIPS32: $v0 = COPY [[SELECT]](p0)
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; MIPS32: RetRA implicit $v0
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%3:_(s32) = COPY $a0
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%0:_(s1) = G_TRUNC %3(s32)
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%1:_(p0) = COPY $a1
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%2:_(p0) = COPY $a2
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%4:_(p0) = G_SELECT %0(s1), %1, %2
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$v0 = COPY %4(p0)
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RetRA implicit $v0
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...
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---
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name: select_with_negation
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: select_with_negation
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[COPY5]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]]
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; MIPS32: $v0 = COPY [[SELECT]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = COPY $a2
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%3:_(s32) = COPY $a3
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%5:_(s1) = G_CONSTANT i1 true
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%4:_(s1) = G_ICMP intpred(slt), %0(s32), %1
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%6:_(s1) = G_XOR %4, %5
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%7:_(s32) = G_SELECT %6(s1), %2, %3
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$v0 = COPY %7(s32)
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RetRA implicit $v0
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...
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83
test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
Normal file
83
test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
Normal file
@ -0,0 +1,83 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
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define i8 @select_i8(i1 %test, i8 %a, i8 %b) {
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; MIPS32-LABEL: select_i8:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 0
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; MIPS32-NEXT: ori $1, $1, 1
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; MIPS32-NEXT: and $1, $4, $1
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; MIPS32-NEXT: movn $6, $5, $1
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; MIPS32-NEXT: move $2, $6
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%cond = select i1 %test, i8 %a, i8 %b
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ret i8 %cond
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}
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define i16 @select_i16(i1 %test, i16 %a, i16 %b) {
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; MIPS32-LABEL: select_i16:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 0
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; MIPS32-NEXT: ori $1, $1, 1
|
||||
; MIPS32-NEXT: and $1, $4, $1
|
||||
; MIPS32-NEXT: movn $6, $5, $1
|
||||
; MIPS32-NEXT: move $2, $6
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%cond = select i1 %test, i16 %a, i16 %b
|
||||
ret i16 %cond
|
||||
}
|
||||
|
||||
define i32 @select_i32(i1 %test, i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: select_i32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, 0
|
||||
; MIPS32-NEXT: ori $1, $1, 1
|
||||
; MIPS32-NEXT: and $1, $4, $1
|
||||
; MIPS32-NEXT: movn $6, $5, $1
|
||||
; MIPS32-NEXT: move $2, $6
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%cond = select i1 %test, i32 %a, i32 %b
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
define i32* @select_ptr(i1 %test, i32* %a, i32* %b) {
|
||||
; MIPS32-LABEL: select_ptr:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, 0
|
||||
; MIPS32-NEXT: ori $1, $1, 1
|
||||
; MIPS32-NEXT: and $1, $4, $1
|
||||
; MIPS32-NEXT: movn $6, $5, $1
|
||||
; MIPS32-NEXT: move $2, $6
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%cond = select i1 %test, i32* %a, i32* %b
|
||||
ret i32* %cond
|
||||
}
|
||||
|
||||
define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
|
||||
; MIPS32-LABEL: select_with_negation:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, 65535
|
||||
; MIPS32-NEXT: ori $1, $1, 65535
|
||||
; MIPS32-NEXT: slt $4, $4, $5
|
||||
; MIPS32-NEXT: xor $1, $4, $1
|
||||
; MIPS32-NEXT: lui $4, 0
|
||||
; MIPS32-NEXT: ori $4, $4, 1
|
||||
; MIPS32-NEXT: and $1, $1, $4
|
||||
; MIPS32-NEXT: movn $7, $6, $1
|
||||
; MIPS32-NEXT: move $2, $7
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%cmp = icmp slt i32 %a, %b
|
||||
%lneg = xor i1 %cmp, true
|
||||
%cond = select i1 %lneg, i32 %x, i32 %y
|
||||
ret i32 %cond
|
||||
}
|
||||
70
test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
Normal file
70
test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
Normal file
@ -0,0 +1,70 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
--- |
|
||||
|
||||
define void @select_i32(i32, i32) {entry: ret void}
|
||||
define void @select_ptr(i32, i32) {entry: ret void}
|
||||
|
||||
...
|
||||
---
|
||||
name: select_i32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; MIPS32-LABEL: name: select_i32
|
||||
; MIPS32: liveins: $a0, $a1, $a2
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
|
||||
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
|
||||
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
|
||||
; MIPS32: $v0 = COPY [[SELECT]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
%3:_(s32) = COPY $a0
|
||||
%1:_(s32) = COPY $a1
|
||||
%2:_(s32) = COPY $a2
|
||||
%6:_(s32) = G_CONSTANT i32 1
|
||||
%7:_(s32) = COPY %3(s32)
|
||||
%5:_(s32) = G_AND %7, %6
|
||||
%4:_(s32) = G_SELECT %5(s32), %1, %2
|
||||
$v0 = COPY %4(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: select_ptr
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; MIPS32-LABEL: name: select_ptr
|
||||
; MIPS32: liveins: $a0, $a1, $a2
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
|
||||
; MIPS32: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
|
||||
; MIPS32: $v0 = COPY [[SELECT]](p0)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
%3:_(s32) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%6:_(s32) = G_CONSTANT i32 1
|
||||
%7:_(s32) = COPY %3(s32)
|
||||
%5:_(s32) = G_AND %7, %6
|
||||
%4:_(p0) = G_SELECT %5(s32), %1, %2
|
||||
$v0 = COPY %4(p0)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user