RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Code Issues Projects Releases Wiki Activity

Make psuedo FEXT_T8I816_ins a custom inserter. It should be expanded

Browse Source 
as early as possible; which means during instruction selection.

llvm-svn: 175984
This commit is contained in:
Reed Kotler 2013-02-24 06:16:39 +00:00
parent 3ee02ffe83
commit 407e5b31f6
4 changed files with 34 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -135,48 +135,26 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
switch(MI->getDesc().getOpcode()) {
default:
return false;
case Mips::BteqzT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
break;
case Mips::BteqzT8CmpiX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
break;
case Mips::BteqzT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
break;
case Mips::BteqzT8SltiX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
Mips::SltiRxImm16, Mips::SltiRxImmX16);
break;
case Mips::BteqzT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
break;
case Mips::BteqzT8SltiuX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
break;
case Mips::BtnezT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
break;
case Mips::BtnezT8CmpiX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
break;
case Mips::BtnezT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
break;
case Mips::BtnezT8SltiX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
Mips::SltiRxImm16, Mips::SltiRxImmX16);
break;
case Mips::BtnezT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16);
break;
case Mips::BtnezT8SltiuX16:
ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
Mips::SltiuRxImm16, Mips::SltiuRxImmX16);

1
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -225,6 +225,7 @@ class FEXT_T8I816_ins<string asmstr, string asmstr2>:
!strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
!strconcat(asmstr, "\t$imm"))),[]> {
let isCodeGenOnly=1;
let usesCustomInserter = 1;
}
//

30
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -1429,6 +1429,20 @@ MachineBasicBlock *MipsTargetLowering::EmitSeliT16
}
MachineBasicBlock
*MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
MachineInstr *MI,
MachineBasicBlock *BB) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned regX = MI->getOperand(0).getReg();
unsigned regY = MI->getOperand(1).getReg();
MachineBasicBlock *target = MI->getOperand(2).getMBB();
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
MachineBasicBlock *
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const {
@ -1568,6 +1582,22 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
case Mips::SelTBtneZSltu:
return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
case Mips::BteqzT8CmpX16:
return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
case Mips::BteqzT8SltX16:
return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
case Mips::BteqzT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
case Mips::BtnezT8CmpX16:
return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
case Mips::BtnezT8SltX16:
return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
case Mips::BtnezT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
}
}

3
lib/Target/Mips/MipsISelLowering.h
View File

@ -413,6 +413,9 @@ namespace llvm {
MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
MachineInstr *MI,
MachineBasicBlock *BB) const;
MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
MachineInstr *MI,
MachineBasicBlock *BB) const;
};
}