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AArch64/PEI: Do not add reserved regs to liveins

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We do not track liveness for reserved registers. It is unnecessary to
add them to block livein lists.

llvm-svn: 304059
This commit is contained in:
Matthias Braun 2017-05-27 03:38:02 +00:00
parent c05ac10abe
commit 40877e1e1e
3 changed files with 9 additions and 5 deletions
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3
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -450,12 +450,13 @@ static void updateLiveness(MachineFunction &MF) {
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
for (MachineBasicBlock *MBB : Visited) {
MCPhysReg Reg = CSI[i].getReg();
// Add the callee-saved register as live-in.
// It's killed at the spill.
if (!MBB->isLiveIn(Reg))
if (!MRI.isReserved(Reg) && !MBB->isLiveIn(Reg))
MBB->addLiveIn(Reg);
}
}

7
lib/Target/AArch64/AArch64FrameLowering.cpp
View File

@ -991,6 +991,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
SmallVector<RegPairInfo, 8> RegPairs;
computeCalleeSaveRegisterPairs(MF, CSI, TRI, RegPairs);
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (auto RPII = RegPairs.rbegin(), RPIE = RegPairs.rend(); RPII != RPIE;
++RPII) {
@ -1022,9 +1023,11 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
dbgs() << ")\n");
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
MBB.addLiveIn(Reg1);
if (!MRI.isReserved(Reg1))
MBB.addLiveIn(Reg1);
if (RPI.isPaired()) {
MBB.addLiveIn(Reg2);
if (!MRI.isReserved(Reg2))
MBB.addLiveIn(Reg2);
MIB.addReg(Reg2, getPrologueDeath(MF, Reg2));
MIB.addMemOperand(MF.getMachineMemOperand(
MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),

4
test/CodeGen/AArch64/live-interval-analysis.mir
View File

@ -6,7 +6,7 @@
---
# CHECK-LABEL: ********** INTERVALS **********
# W29 is reserved, so we should only see dead defs
# CHECK-DAG: W29 [0B,0d:{{[0-9]+}})[32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}})
# CHECK-DAG: W29 [32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}})
# For normal registers like x28 we should see the full intervals
# CHECK-DAG: W28 [0B,16r:{{[0-9]+}})[32r,48r:{{[0-9]+}})[48r,48d:{{[0-9]+}})
# CHECK: # End machine code for function reserved_reg_liveness.
@ -14,7 +14,7 @@ name: reserved_reg_liveness
tracksRegLiveness: true
body: |
bb.0:
liveins: %x28_fp
liveins: %x28
%6 : xseqpairsclass = COPY %x28_fp
%x28_fp = COPY %6
%x28 = COPY %x28