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Improve ISel across lane float min/max reduction
In vectorized float min/max reduction code, the final "reduce" step is sub-optimal. In AArch64, this change wll combine : svn0 = vector_shuffle t0, undef<2,3,u,u> fmin = fminnum t0,svn0 svn1 = vector_shuffle fmin, undef<1,u,u,u> cc = setcc fmin, svn1, ole n0 = extract_vector_elt cc, #0 n1 = extract_vector_elt fmin, #0 n2 = extract_vector_elt fmin, #1 result = select n0, n1,n2 into : result = llvm.aarch64.neon.fminnmv t0 This change extends r247575. llvm-svn: 249834
This commit is contained in:
Jun Bum Lim
parent
25e088eb37
commit
40a541ec25
@ -8750,8 +8750,13 @@ static SDValue tryMatchAcrossLaneShuffleForReduction(SDNode *N, SDValue OpV,
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return SDValue();
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int NumVecElts = VTy.getVectorNumElements();
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if (NumVecElts != 4 && NumVecElts != 8 && NumVecElts != 16)
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return SDValue();
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if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
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if (NumVecElts != 4)
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return SDValue();
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} else {
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if (NumVecElts != 4 && NumVecElts != 8 && NumVecElts != 16)
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return SDValue();
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}
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int NumExpectedSteps = APInt(8, NumVecElts).logBase2();
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SDValue PreOp = OpV;
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@ -8802,6 +8807,8 @@ static SDValue tryMatchAcrossLaneShuffleForReduction(SDNode *N, SDValue OpV,
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PreOp = CurOp;
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}
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unsigned Opcode;
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bool IsIntrinsic = false;
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switch (Op) {
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default:
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llvm_unreachable("Unexpected operator for across vector reduction");
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@ -8820,11 +8827,24 @@ static SDValue tryMatchAcrossLaneShuffleForReduction(SDNode *N, SDValue OpV,
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case ISD::UMIN:
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Opcode = AArch64ISD::UMINV;
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break;
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case ISD::FMAXNUM:
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Opcode = Intrinsic::aarch64_neon_fmaxnmv;
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IsIntrinsic = true;
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break;
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case ISD::FMINNUM:
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Opcode = Intrinsic::aarch64_neon_fminnmv;
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IsIntrinsic = true;
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break;
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}
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SDLoc DL(N);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0),
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DAG.getNode(Opcode, DL, PreOp.getSimpleValueType(), PreOp),
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DAG.getConstant(0, DL, MVT::i64));
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return IsIntrinsic
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? DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, N->getValueType(0),
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DAG.getConstant(Opcode, DL, MVT::i32), PreOp)
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: DAG.getNode(
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ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0),
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DAG.getNode(Opcode, DL, PreOp.getSimpleValueType(), PreOp),
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DAG.getConstant(0, DL, MVT::i64));
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}
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/// Target-specific DAG combine for the across vector min/max reductions.
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@ -8848,9 +8868,6 @@ static SDValue tryMatchAcrossLaneShuffleForReduction(SDNode *N, SDValue OpV,
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/// becomes :
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/// %1 = smaxv %0
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/// %result = extract_vector_elt %1, 0
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/// FIXME: Currently this function matches only SMAXV, UMAXV, SMINV, and UMINV.
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/// We could also support other types of across lane reduction available
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/// in AArch64, including FMAXNMV, FMAXV, FMINNMV, and FMINV.
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static SDValue
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performAcrossLaneMinMaxReductionCombine(SDNode *N, SelectionDAG &DAG,
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const AArch64Subtarget *Subtarget) {
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@ -8878,17 +8895,26 @@ performAcrossLaneMinMaxReductionCombine(SDNode *N, SelectionDAG &DAG,
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SDValue VectorOp = SetCC.getOperand(0);
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unsigned Op = VectorOp->getOpcode();
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// Check if the input vector is fed by the operator we want to handle.
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if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN && Op != ISD::UMIN)
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if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN &&
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Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM)
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return SDValue();
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EVT VTy = VectorOp.getValueType();
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if (!VTy.isVector())
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return SDValue();
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EVT EltTy = VTy.getVectorElementType();
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if (EltTy != MVT::i32 && EltTy != MVT::i16 && EltTy != MVT::i8)
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if (VTy.getSizeInBits() < 64)
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return SDValue();
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EVT EltTy = VTy.getVectorElementType();
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if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
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if (EltTy != MVT::f32)
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return SDValue();
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} else {
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if (EltTy != MVT::i32 && EltTy != MVT::i16 && EltTy != MVT::i8)
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return SDValue();
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}
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// Check if extracting from the same vector.
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// For example,
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// %sc = setcc %vector, %svn1, gt
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@ -8904,7 +8930,13 @@ performAcrossLaneMinMaxReductionCombine(SDNode *N, SelectionDAG &DAG,
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if ((Op == ISD::SMAX && CC != ISD::SETGT && CC != ISD::SETGE) ||
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(Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) ||
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(Op == ISD::SMIN && CC != ISD::SETLT && CC != ISD::SETLE) ||
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(Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE))
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(Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) ||
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(Op == ISD::FMAXNUM && CC != ISD::SETOGT && CC != ISD::SETOGE &&
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CC != ISD::SETUGT && CC != ISD::SETUGE && CC != ISD::SETGT &&
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CC != ISD::SETGE) ||
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(Op == ISD::FMINNUM && CC != ISD::SETOLT && CC != ISD::SETOLE &&
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CC != ISD::SETULT && CC != ISD::SETULE && CC != ISD::SETLT &&
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CC != ISD::SETLE))
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return SDValue();
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// Expect to check only lane 0 from the vector SETCC.
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@ -8963,6 +8995,9 @@ performAcrossLaneAddReductionCombine(SDNode *N, SelectionDAG &DAG,
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if (EltTy != MVT::i32 && EltTy != MVT::i16 && EltTy != MVT::i8)
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return SDValue();
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if (VTy.getSizeInBits() < 64)
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return SDValue();
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return tryMatchAcrossLaneShuffleForReduction(N, N0, ISD::ADD, DAG);
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}
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@ -285,3 +285,35 @@ define i64 @umin_D(<2 x i64>* nocapture readonly %arr) {
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%r = select i1 %rdx.minmax.cmp18.elt, i64 %rdx.minmax.select.elt, i64 %rdx.shuf.elt
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ret i64 %r
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}
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; CHECK-LABEL: f_fmaxnmv
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; CHECK: fmaxnmv
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define float @f_fmaxnmv(<4 x float>* nocapture readonly %arr) {
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%rdx.minmax.select = load <4 x float>, <4 x float>* %arr
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%rdx.shuf = shufflevector <4 x float> %rdx.minmax.select, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%rdx.minmax.cmp = fcmp fast oge <4 x float> %rdx.minmax.select, %rdx.shuf
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%rdx.minmax.select1 = select <4 x i1> %rdx.minmax.cmp, <4 x float> %rdx.minmax.select, <4 x float> %rdx.shuf
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%rdx.shuf1 = shufflevector <4 x float> %rdx.minmax.select1, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%rdx.minmax.cmp1 = fcmp fast oge <4 x float> %rdx.minmax.select1, %rdx.shuf1
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%rdx.minmax.cmp1.elt = extractelement <4 x i1> %rdx.minmax.cmp1, i32 0
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%rdx.minmax.select1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 0
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%rdx.shuf1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 1
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%r = select i1 %rdx.minmax.cmp1.elt, float %rdx.minmax.select1.elt, float %rdx.shuf1.elt
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ret float %r
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}
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; CHECK-LABEL: f_fminnmv
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; CHECK: fminnmv
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define float @f_fminnmv(<4 x float>* nocapture readonly %arr) {
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%rdx.minmax.select = load <4 x float>, <4 x float>* %arr
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%rdx.shuf = shufflevector <4 x float> %rdx.minmax.select, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%rdx.minmax.cmp = fcmp fast ole <4 x float> %rdx.minmax.select, %rdx.shuf
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%rdx.minmax.select1 = select <4 x i1> %rdx.minmax.cmp, <4 x float> %rdx.minmax.select, <4 x float> %rdx.shuf
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%rdx.shuf1 = shufflevector <4 x float> %rdx.minmax.select1, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%rdx.minmax.cmp1 = fcmp fast ole <4 x float> %rdx.minmax.select1, %rdx.shuf1
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%rdx.minmax.cmp1.elt = extractelement <4 x i1> %rdx.minmax.cmp1, i32 0
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%rdx.minmax.select1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 0
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%rdx.shuf1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 1
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%r = select i1 %rdx.minmax.cmp1.elt, float %rdx.minmax.select1.elt, float %rdx.shuf1.elt
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ret float %r
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}
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