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Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE
out of X86ISelDAGToDAG.cpp C++ code and into tablegen code. Among other things, using tablegen for these things makes them friendlier to FastISel. Tablegen can handle the case of i8 subregs on x86-32, but currently the C++ code for that case uses MVT::Flag in a tricky way, and it happens to schedule better in some cases. So for now, leave the C++ code in place to handle the i8 case on x86-32. llvm-svn: 55078
This commit is contained in:
Dan Gohman
parent
50af19179b
commit
411cc551cb
@ -234,9 +234,11 @@ namespace {
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/// base register. Return the virtual register that holds this value.
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SDNode *getGlobalBaseReg();
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/// getTruncate - return an SDNode that implements a subreg based truncate
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/// of the specified operand to the the specified value type.
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SDNode *getTruncate(SDValue N0, MVT VT);
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/// getTruncateTo8Bit - return an SDNode that implements a subreg based
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/// truncate of the specified operand to i8. This can be done with tablegen,
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/// except that this code uses MVT::Flag in a tricky way that happens to
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/// improve scheduling in some cases.
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SDNode *getTruncateTo8Bit(SDValue N0);
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#ifndef NDEBUG
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unsigned Indent;
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@ -1133,38 +1135,33 @@ static SDNode *FindCallStartFromCall(SDNode *Node) {
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return FindCallStartFromCall(Node->getOperand(0).Val);
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}
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SDNode *X86DAGToDAGISel::getTruncate(SDValue N0, MVT VT) {
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SDValue SRIdx;
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switch (VT.getSimpleVT()) {
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default: assert(0 && "Unknown truncate!");
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case MVT::i8:
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SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
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// Ensure that the source register has an 8-bit subreg on 32-bit targets
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if (!Subtarget->is64Bit()) {
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unsigned Opc;
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MVT N0VT = N0.getValueType();
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switch (N0VT.getSimpleVT()) {
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default: assert(0 && "Unknown truncate!");
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case MVT::i16:
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Opc = X86::MOV16to16_;
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break;
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case MVT::i32:
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Opc = X86::MOV32to32_;
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break;
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}
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N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
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return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
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VT, N0, SRIdx, N0.getValue(1));
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}
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break;
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case MVT::i16:
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SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
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break;
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case MVT::i32:
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SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
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break;
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}
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return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, VT, N0, SRIdx);
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/// getTruncateTo8Bit - return an SDNode that implements a subreg based
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/// truncate of the specified operand to i8. This can be done with tablegen,
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/// except that this code uses MVT::Flag in a tricky way that happens to
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/// improve scheduling in some cases.
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SDNode *X86DAGToDAGISel::getTruncateTo8Bit(SDValue N0) {
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assert(!Subtarget->is64Bit() &&
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"getTruncateTo8Bit is only needed on x86-32!");
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SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
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// Ensure that the source register has an 8-bit subreg on 32-bit targets
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unsigned Opc;
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MVT N0VT = N0.getValueType();
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switch (N0VT.getSimpleVT()) {
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default: assert(0 && "Unknown truncate!");
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case MVT::i16:
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Opc = X86::MOV16to16_;
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break;
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case MVT::i32:
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Opc = X86::MOV32to32_;
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break;
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}
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// The use of MVT::Flag here is not strictly accurate, but it helps
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// scheduling in some cases.
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N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
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return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
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MVT::i8, N0, SRIdx, N0.getValue(1));
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}
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@ -1507,90 +1504,45 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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return NULL;
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}
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case ISD::ANY_EXTEND: {
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// Check if the type extended to supports subregs.
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if (NVT == MVT::i8)
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break;
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SDValue N0 = Node->getOperand(0);
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// Get the subregsiter index for the type to extend.
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MVT N0VT = N0.getValueType();
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// FIXME: In x86-32, 8-bit value may be in AH, etc. which don't have
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// super-registers.
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unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT :
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(N0VT == MVT::i16) ? X86::SUBREG_16BIT :
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(Subtarget->is64Bit()) ? X86::SUBREG_8BIT : 0;
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// If we don't have a subreg Idx, let generated ISel have a try.
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if (Idx == 0)
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break;
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// If we have an index, generate an insert_subreg into undef.
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AddToISelQueue(N0);
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SDValue Undef =
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SDValue(CurDAG->getTargetNode(X86::IMPLICIT_DEF, NVT), 0);
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SDValue SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32);
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SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
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NVT, Undef, N0, SRIdx);
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(ResNode->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return ResNode;
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}
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case ISD::SIGN_EXTEND_INREG: {
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SDValue N0 = Node->getOperand(0);
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AddToISelQueue(N0);
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MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
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SDValue TruncOp = SDValue(getTruncate(N0, SVT), 0);
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unsigned Opc = 0;
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switch (NVT.getSimpleVT()) {
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default: assert(0 && "Unknown sign_extend_inreg!");
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case MVT::i16:
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if (SVT == MVT::i8) Opc = X86::MOVSX16rr8;
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else assert(0 && "Unknown sign_extend_inreg!");
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break;
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case MVT::i32:
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switch (SVT.getSimpleVT()) {
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default: assert(0 && "Unknown sign_extend_inreg!");
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case MVT::i8: Opc = X86::MOVSX32rr8; break;
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case MVT::i16: Opc = X86::MOVSX32rr16; break;
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}
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break;
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case MVT::i64:
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switch (SVT.getSimpleVT()) {
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default: assert(0 && "Unknown sign_extend_inreg!");
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case MVT::i8: Opc = X86::MOVSX64rr8; break;
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case MVT::i16: Opc = X86::MOVSX64rr16; break;
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case MVT::i32: Opc = X86::MOVSX64rr32; break;
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}
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break;
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}
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if (SVT == MVT::i8 && !Subtarget->is64Bit()) {
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SDValue N0 = Node->getOperand(0);
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AddToISelQueue(N0);
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SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
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SDValue TruncOp = SDValue(getTruncateTo8Bit(N0), 0);
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unsigned Opc = 0;
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switch (NVT.getSimpleVT()) {
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default: assert(0 && "Unknown sign_extend_inreg!");
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case MVT::i16:
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Opc = X86::MOVSX16rr8;
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break;
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case MVT::i32:
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Opc = X86::MOVSX32rr8;
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break;
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}
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SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(TruncOp.Val->dump(CurDAG));
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DOUT << "\n";
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(ResNode->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(TruncOp.Val->dump(CurDAG));
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DOUT << "\n";
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(ResNode->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return ResNode;
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return ResNode;
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}
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break;
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}
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case ISD::TRUNCATE: {
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SDValue Input = Node->getOperand(0);
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AddToISelQueue(Node->getOperand(0));
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SDNode *ResNode = getTruncate(Input, NVT);
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if (NVT == MVT::i8 && !Subtarget->is64Bit()) {
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SDValue Input = Node->getOperand(0);
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AddToISelQueue(Node->getOperand(0));
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SDNode *ResNode = getTruncateTo8Bit(Input);
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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@ -1598,7 +1550,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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DOUT << "\n";
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Indent -= 2;
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#endif
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return ResNode;
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return ResNode;
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}
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break;
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}
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@ -1254,24 +1254,40 @@ def : Pat<(i64 (zext GR32:$src)),
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def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
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// extload
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def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
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def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
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def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
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def : Pat<(extloadi64i32 addr:$src),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
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x86_subreg_32bit)>;
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def : Pat<(extloadi64i1 addr:$src),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src),
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x86_subreg_8bit)>;
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def : Pat<(extloadi64i8 addr:$src),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src),
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x86_subreg_8bit)>;
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def : Pat<(extloadi64i16 addr:$src),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV16rm addr:$src),
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x86_subreg_16bit)>;
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def : Pat<(extloadi64i32 addr:$src),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
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x86_subreg_32bit)>;
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def : Pat<(extloadi16i1 addr:$src),
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(INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
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x86_subreg_8bit)>,
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Requires<[In64BitMode]>;
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def : Pat<(extloadi16i8 addr:$src),
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(INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
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x86_subreg_8bit)>,
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Requires<[In64BitMode]>;
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// anyext -> zext
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def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
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def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>;
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// anyext
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def : Pat<(i64 (anyext GR8:$src)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
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def : Pat<(i64 (anyext GR16:$src)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
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def : Pat<(i64 (anyext GR32:$src)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
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def : Pat<(i64 (anyext (loadi8 addr:$src))), (MOVZX64rm8 addr:$src)>;
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def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr:$src)>;
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def : Pat<(i64 (anyext (loadi32 addr:$src))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
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x86_subreg_32bit)>;
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def : Pat<(i16 (anyext GR8:$src)),
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(INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
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Requires<[In64BitMode]>;
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def : Pat<(i32 (anyext GR8:$src)),
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(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
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Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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// Some peepholes
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@ -1295,6 +1311,34 @@ def : Pat<(and GR16:$src1, 0xff),
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(MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
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Requires<[In64BitMode]>;
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// sext_inreg patterns
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def : Pat<(sext_inreg GR64:$src, i32),
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(MOVSX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
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def : Pat<(sext_inreg GR64:$src, i16),
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(MOVSX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
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def : Pat<(sext_inreg GR64:$src, i8),
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(MOVSX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
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def : Pat<(sext_inreg GR32:$src, i8),
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(MOVSX32rr8 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)))>,
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Requires<[In64BitMode]>;
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def : Pat<(sext_inreg GR16:$src, i8),
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(MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
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Requires<[In64BitMode]>;
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// trunc patterns
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def : Pat<(i32 (trunc GR64:$src)),
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(i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
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def : Pat<(i16 (trunc GR64:$src)),
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(i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
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def : Pat<(i8 (trunc GR64:$src)),
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(i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
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def : Pat<(i8 (trunc GR32:$src)),
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(i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
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Requires<[In64BitMode]>;
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def : Pat<(i8 (trunc GR16:$src)),
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(i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit))>,
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Requires<[In64BitMode]>;
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// (shl x, 1) ==> (add x, x)
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def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
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@ -2784,19 +2784,21 @@ def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
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// extload bool -> extload byte
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def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
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def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
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def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
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Requires<[In32BitMode]>;
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def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
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def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
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def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
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Requires<[In32BitMode]>;
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def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
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def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
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// anyext -> zext
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def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
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def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
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def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
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def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
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def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
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def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
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// anyext
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def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
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Requires<[In32BitMode]>;
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def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
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Requires<[In32BitMode]>;
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def : Pat<(i32 (anyext GR16:$src)),
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(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
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// (and (i32 load), 255) -> (zextload i8)
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def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
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@ -2808,16 +2810,38 @@ def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
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// r & (2^16-1) ==> movz
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def : Pat<(and GR32:$src1, 0xffff),
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(MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
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(MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
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// r & (2^8-1) ==> movz
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def : Pat<(and GR32:$src1, 0xff),
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(MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
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x86_subreg_8bit)))>,
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(MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
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x86_subreg_8bit)))>,
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Requires<[In32BitMode]>;
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// r & (2^8-1) ==> movz
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def : Pat<(and GR16:$src1, 0xff),
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(MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
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x86_subreg_8bit)))>,
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(MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
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x86_subreg_8bit)))>,
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Requires<[In32BitMode]>;
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// sext_inreg patterns
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def : Pat<(sext_inreg GR32:$src, i16),
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(MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
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def : Pat<(sext_inreg GR32:$src, i8),
|
||||
(MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
|
||||
x86_subreg_8bit)))>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : Pat<(sext_inreg GR16:$src, i8),
|
||||
(MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
|
||||
x86_subreg_8bit)))>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
// trunc patterns
|
||||
def : Pat<(i16 (trunc GR32:$src)),
|
||||
(i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
|
||||
def : Pat<(i8 (trunc GR32:$src)),
|
||||
(i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : Pat<(i8 (trunc GR16:$src)),
|
||||
(i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
// (shl x, 1) ==> (add x, x)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user