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[X86] Remove sse4.1 intrinsic tests from the avx intrinsics test file.
They are all covered by the SSE4.1 intrinsics test with SSE4.1, AVX, and AVX512 command lines. llvm-svn: 295706
This commit is contained in:
Craig Topper
parent
528d3b1e15
commit
41277d7d7e
@ -2,345 +2,6 @@
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; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx,aes,pclmul -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
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define <2 x double> @test_x86_sse41_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
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; CHECK-LABEL: test_x86_sse41_blendvpd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x4b,0xc1,0x20]
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; CHECK-NEXT: retl ## encoding: [0xc3]
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%res = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
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define <4 x float> @test_x86_sse41_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
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; CHECK-LABEL: test_x86_sse41_blendvps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x4a,0xc1,0x20]
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; CHECK-NEXT: retl ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
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define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK-LABEL: test_x86_sse41_dppd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vdppd $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x41,0xc1,0x07]
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; CHECK-NEXT: retl ## encoding: [0xc3]
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%res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwind readnone
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define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK-LABEL: test_x86_sse41_dpps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x40,0xc1,0x07]
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; CHECK-NEXT: retl ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind readnone
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define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) {
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; AVX-LABEL: test_x86_sse41_insertps:
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; AVX: ## BB#0:
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; AVX-NEXT: vinsertps $21, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x15]
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; AVX-NEXT: ## xmm0 = zero,xmm1[0],zero,xmm0[3]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_insertps:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vinsertps $21, %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x21,0xc1,0x15]
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; AVX512VL-NEXT: ## xmm0 = zero,xmm1[0],zero,xmm0[3]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 21) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
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define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: test_x86_sse41_mpsadbw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmpsadbw $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x42,0xc1,0x07]
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; CHECK-NEXT: retl ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind readnone
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define <8 x i16> @test_x86_sse41_packusdw(<4 x i32> %a0, <4 x i32> %a1) {
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; AVX-LABEL: test_x86_sse41_packusdw:
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; AVX: ## BB#0:
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; AVX-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x2b,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_packusdw:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x2b,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
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define <16 x i8> @test_x86_sse41_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
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; CHECK-LABEL: test_x86_sse41_pblendvb:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x4c,0xc1,0x20]
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; CHECK-NEXT: retl ## encoding: [0xc3]
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%res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
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define <8 x i16> @test_x86_sse41_phminposuw(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_sse41_phminposuw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vphminposuw %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x41,0xc0]
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; CHECK-NEXT: retl ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16>) nounwind readnone
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define <16 x i8> @test_x86_sse41_pmaxsb(<16 x i8> %a0, <16 x i8> %a1) {
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; AVX-LABEL: test_x86_sse41_pmaxsb:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x3c,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pmaxsb:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x3c,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone
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define <4 x i32> @test_x86_sse41_pmaxsd(<4 x i32> %a0, <4 x i32> %a1) {
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; AVX-LABEL: test_x86_sse41_pmaxsd:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x3d,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pmaxsd:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x3d,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_x86_sse41_pmaxud(<4 x i32> %a0, <4 x i32> %a1) {
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; AVX-LABEL: test_x86_sse41_pmaxud:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x3f,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pmaxud:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x3f,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
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define <8 x i16> @test_x86_sse41_pmaxuw(<8 x i16> %a0, <8 x i16> %a1) {
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; AVX-LABEL: test_x86_sse41_pmaxuw:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x3e,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pmaxuw:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x3e,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone
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define <16 x i8> @test_x86_sse41_pminsb(<16 x i8> %a0, <16 x i8> %a1) {
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; AVX-LABEL: test_x86_sse41_pminsb:
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; AVX: ## BB#0:
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; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x38,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pminsb:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x38,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone
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define <4 x i32> @test_x86_sse41_pminsd(<4 x i32> %a0, <4 x i32> %a1) {
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; AVX-LABEL: test_x86_sse41_pminsd:
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; AVX: ## BB#0:
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; AVX-NEXT: vpminsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x39,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pminsd:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpminsd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x39,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_x86_sse41_pminud(<4 x i32> %a0, <4 x i32> %a1) {
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; AVX-LABEL: test_x86_sse41_pminud:
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; AVX: ## BB#0:
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; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x3b,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pminud:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpminud %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x3b,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
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define <8 x i16> @test_x86_sse41_pminuw(<8 x i16> %a0, <8 x i16> %a1) {
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; AVX-LABEL: test_x86_sse41_pminuw:
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; AVX: ## BB#0:
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; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x3a,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pminuw:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x3a,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
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define <2 x i64> @test_x86_sse41_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
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; AVX-LABEL: test_x86_sse41_pmuldq:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x28,0xc1]
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; AVX-NEXT: retl ## encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_sse41_pmuldq:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x28,0xc1]
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; AVX512VL-NEXT: retl ## encoding: [0xc3]
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%res = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
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define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) {
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; CHECK-LABEL: test_x86_sse41_ptestc:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vptest %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x17,0xc1]
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; CHECK-NEXT: sbbl %eax, %eax ## encoding: [0x19,0xc0]
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; CHECK-NEXT: andl $1, %eax ## encoding: [0x83,0xe0,0x01]
|
||||
; CHECK-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
|
||||
|
||||
|
||||
define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) {
|
||||
; CHECK-LABEL: test_x86_sse41_ptestnzc:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
|
||||
; CHECK-NEXT: vptest %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x17,0xc1]
|
||||
; CHECK-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
|
||||
; CHECK-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
|
||||
|
||||
|
||||
define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) {
|
||||
; CHECK-LABEL: test_x86_sse41_ptestz:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
|
||||
; CHECK-NEXT: vptest %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x17,0xc1]
|
||||
; CHECK-NEXT: sete %al ## encoding: [0x0f,0x94,0xc0]
|
||||
; CHECK-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
|
||||
|
||||
|
||||
define <2 x double> @test_x86_sse41_round_pd(<2 x double> %a0) {
|
||||
; CHECK-LABEL: test_x86_sse41_round_pd:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vroundpd $7, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x09,0xc0,0x07]
|
||||
; CHECK-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
}
|
||||
declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
|
||||
|
||||
|
||||
define <4 x float> @test_x86_sse41_round_ps(<4 x float> %a0) {
|
||||
; CHECK-LABEL: test_x86_sse41_round_ps:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vroundps $7, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x08,0xc0,0x07]
|
||||
; CHECK-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
|
||||
|
||||
|
||||
define <2 x double> @test_x86_sse41_round_sd(<2 x double> %a0, <2 x double> %a1) {
|
||||
; CHECK-LABEL: test_x86_sse41_round_sd:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0b,0xc1,0x07]
|
||||
; CHECK-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
}
|
||||
declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
|
||||
|
||||
|
||||
define <4 x float> @test_x86_sse41_round_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK-LABEL: test_x86_sse41_round_ss:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vroundss $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0a,0xc1,0x07]
|
||||
; CHECK-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
|
||||
|
||||
|
||||
define i32 @test_x86_sse42_pcmpestri128(<16 x i8> %a0, <16 x i8> %a2) {
|
||||
; CHECK-LABEL: test_x86_sse42_pcmpestri128:
|
||||
; CHECK: ## BB#0:
|
||||
@ -1882,8 +1543,8 @@ define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind {
|
||||
; AVX-LABEL: movnt_dq:
|
||||
; AVX: ## BB#0:
|
||||
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
|
||||
; AVX-NEXT: vpaddq LCPI127_0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
|
||||
; AVX-NEXT: ## fixup A - offset: 4, value: LCPI127_0, kind: FK_Data_4
|
||||
; AVX-NEXT: vpaddq LCPI102_0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
|
||||
; AVX-NEXT: ## fixup A - offset: 4, value: LCPI102_0, kind: FK_Data_4
|
||||
; AVX-NEXT: vmovntdq %ymm0, (%eax) ## encoding: [0xc5,0xfd,0xe7,0x00]
|
||||
; AVX-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
|
||||
; AVX-NEXT: retl ## encoding: [0xc3]
|
||||
@ -1891,8 +1552,8 @@ define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind {
|
||||
; AVX512VL-LABEL: movnt_dq:
|
||||
; AVX512VL: ## BB#0:
|
||||
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
|
||||
; AVX512VL-NEXT: vpaddq LCPI127_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
|
||||
; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI127_0, kind: FK_Data_4
|
||||
; AVX512VL-NEXT: vpaddq LCPI102_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A]
|
||||
; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI102_0, kind: FK_Data_4
|
||||
; AVX512VL-NEXT: vmovntdq %ymm0, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe7,0x00]
|
||||
; AVX512VL-NEXT: retl ## encoding: [0xc3]
|
||||
%a2 = add <2 x i64> %a1, <i64 1, i64 1>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user